Hot Swappable Level Translating I²C-Bus Repeater

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Block Diagram

PCA9508 Block Diagram

PCA9508 Block Diagram

Features

  • 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of the device
  • Supports offset-free hot-swap with IDLE/STOP detect circuitry
  • Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
  • Footprint and functional replacement for PCA9515, PCA9515A, PCA9517 and PCA9517A
  • I²C-bus and SMBus compatible
  • Active HIGH repeater enable input
  • Static level offset on B side
  • Open-drain input/outputs
  • Lock-up free operation
  • Supports arbitration and clock stretching across the repeater
  • Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple controllers
  • Powered-off high-impedance I²C-bus pins
  • A side operating supply voltage range of 0.9 V to 5.5 V
  • B side operating supply voltage range of 2.7 V to 5.5 V
  • 5 V tolerant I²C-bus and enable pins
  • 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater).
  • ESD protection exceeds 6000 V HBM per JESD22-A114, 450 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO8 and TSSOP8

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