8-Bit Bidirectional Low-Voltage Translator

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Block Diagram

GTL2003 Block Diagram

GTL2003 Block Diagram

Features

  • 8-bit bidirectional low voltage translator
  • Allows voltage level translation between 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V buses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
  • Provides bidirectional voltage translation with no direction pin
  • Low 6.5 Ω ON-state resistance (Ron) between input and output pins (Sn/Dn)
  • Supports hot insertion
  • No power supply required: will not latch up
  • 5 V tolerant inputs
  • Low standby current
  • Flow-through pinout for ease of printed-circuit board trace routing
  • ESD protection exceeds 2000 V HBM per JESD22-A114, and 1000 V CDM per JESD22-C101
  • Packages offered: TSSOP20, DHVQFN20

Any application that requires bidirectional or unidirectional voltage level translation from any voltage from 0.8 V to 5.0 V to any voltage from 0.8 V to 5.0 V The open-drain construction with no direction pin is ideal for bidirectional low voltage (for example, 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I²C-bus port translation to the normal 3.3 V and/or 5.0 V I²C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels.

  • Any application that requires bidirectional or unidirectional voltage level translation from any voltage from 0.8 V to 5.0 V to any voltage from 0.8 V to 5.0 V
  • The open-drain construction with no direction pin is ideal for bidirectional low voltage (for example, 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I²C-bus port translation to the normal 3.3 V and/or 5.0 V I²C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels.

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