1.8 V dual UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface


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Block Diagram

SC16C852SV Block Diagram

SC16C852SV Block Diagram


  • Dual channel high performance UART
  • 1.8 V operation
  • Advanced package: TFBGA36
  • Up to 20 Mbit/s data rate (4x sampling) at 1.8 V
  • Programmable sampling rate: 16x, 8x, 4x
  • 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
  • 128-byte receive FIFO with error flags to reduce the bandwidth requirement of the external CPU
  • 128 programmable Receive and Transmit FIFO interrupt trigger levels
  • 128 Receive and Transmit FIFO reporting levels (level counters)
  • Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control
  • Programmable Xon/Xoff characters
  • 128 programmable hardware and software trigger levels
  • Automatic 9-bit mode (RS-485) address detection
  • Automatic RS-485 driver turn-around with programmable delay
  • Dual channel concurrent write
  • UART software reset
  • High resolution clock prescaler, from 0 to 15 with granularity of 1/16 to allow non-standard UART clock to be used
  • Industrial temperature range (-40 Cel to +85 Cel)
  • Software compatible with industry standard SC16C652B
  • Software selectable baud rate generator
  • Supports IrDA version 1.0 (up to 115.2 kbit/s)
  • Standard modem interface or infrared IrDA encoder/decoder interface
  • Enhanced Sleep mode and low power feature
  • Modem control functions (CTS, RTS, DTS, DTR, RI, CD)
  • Independent transmitter and receiver enable/disable
  • Pb-free, RoHS compliant package offered


Quick reference to our documentation types.

3 documents

Design Resources

Design Files

1 design file

  • Symbols and Footprints

    SC16C852SVIET-TFBGA36-CAD Symbol and PCB Footprint – BXL File

Engineering Services

3 engineering services

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