13-Bit GTL-/GTL/GTL+ to LVTTL Translator

  • Archived
  • This page contains information on a product that is no longer manufactured (discontinued). Specifications and information herein are available for historical reference only.

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Product Details

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Block Diagram

Block diagram: GTL2006PW

 GTL2006PW Block Diagram


Key Features

  • Operates as a GTL-/GTL/GTL+ to LVTTL sampling receiver or LVTTL to GTL-/GTL/GTL+ driver
  • 3.0 V to 3.6 V operation
  • LVTTL I/O not 5 V tolerant
  • Series termination on the LVTTL outputs of 30 Ω
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 250 V CDM per JESD22-C101
  • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 500 mA
  • Package offered: TSSOP28


Quick reference to our documentation types.

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Design Resources

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Design Files

2 design files

  • Models

    GLT2006 IBIS model

  • Symbols and Footprints

    GTL2006PW_TSSOP28-CAD Symbol and PCB Footprint – BXL File


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