Design Files
2 design files
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Models
IBIS model for MCM69P/F536C
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Models
Core Model for MCM69P536C Verilog model
The MCM69P536C is a 1M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPCTM, 486, i960TM, and PentiumTM microprocessors.
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