12-Bit GTL-/GTL/GTL+-to-LVTTL Translator


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Block Diagram

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GTL2107 Block Diagram

GTL2107 Block Diagram

Block diagram: GTL2107PW


  • Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
  • Operates at GTL, GTL+ or GTL− levels
  • EN1 and EN2 enable control
  • 3.0 V to 3.6 V operation
  • LVTTL I/O not 5 V tolerant
  • Series termination on the LVTTL outputs of 30 Ω
  • ESD protection exceeds 2000 V HBM per JESD22−A114, 150 V MM per JESD22-A115, and 1000 V CDM per JESD22−C101
  • Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds 500 mA
  • Package offered: TSSOP28


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Design Resources

Design Files

2 design files

  • Models

    GLT2107 IBIS model

  • Symbols and Footprints

    GTL2107PW_TSSOP28-CAD Symbol and PCB Footprint – BXL File

Engineering Services

2 engineering services

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