12-Bit GTL-to-LVTTL Translator with Power Good Control and High-Impedance LVTTL and GTL Outputs


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Product Details

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Block Diagram

Block diagram: GTL2008PW


Key Features

  • Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
  • Operates at GTL-/GTL/GTL+ signal levels
  • EN1 and EN2 disable error output
  • All LVTTL and GTL outputs are put in a high-impedance state when EN1 and EN2 are LOW
  • 3.0 V to 3.6 V operation
  • LVTTL I/O not 5 V tolerant
  • Series termination on the LVTTL outputs of 30 O
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds 500 mA
  • Package offered: TSSOP28


Quick reference to our documentation types.

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Design Resources

Design Files

2 design files

  • Models

    GLT2008 IBIS model

  • Symbols and Footprints

    GTL2008PW_TSSOP28-CAD Symbol and PCB Footprint – BXL File

Engineering Services

2 engineering services

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