13-Bit GTL-/GTL/GTL+ to LVTTL Translator

GTL2006PW

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Block Diagram

Block diagram: GTL2006PW

 GTL2006PW Block Diagram

Features

  • Operates as a GTL-/GTL/GTL+ to LVTTL sampling receiver or LVTTL to GTL-/GTL/GTL+ driver
  • 3.0 V to 3.6 V operation
  • LVTTL I/O not 5 V tolerant
  • Series termination on the LVTTL outputs of 30 Ω
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 250 V CDM per JESD22-C101
  • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 500 mA
  • Package offered: TSSOP28

Documentation

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Design Resources

Design Files

2 design files

Engineering Services

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