2-Bit LVTTL-to-GTL Transceiver


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Product Details

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Block Diagram

GTL2012 Block Diagram

GTL2012 Block Diagram


  • Operates as a 2-bit GTL-/GTL/GTL+ sampling receiver or as an LVTTL to GTL-/GTL/GTL+ driver
  • 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
  • GTL input and output 3.6 V tolerant
  • Vref adjustable from 0.5 V to 0.5VCC
  • Partial power-down permitted
  • Latch-up protection exceeds 500 mA per JESD78
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-CC101
  • Package offered: TSSOP8 (MSOP8) and VSSOP8


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Design Resources

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Design Files

2 design files

  • Models

    GLT2012 IBIS model

  • Symbols and Footprints

    GTL2012DP-TSSOP8-CAD Symbol and PCB Footprint – BXL File


2 hardware offerings


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