Design Files
2 design files
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Models
GLT2012 IBIS model
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Symbols and Footprints
GTL2012DP-TSSOP8-CAD Symbol and PCB Footprint – BXL File
2-Bit LVTTL-to-GTL Transceiver
GTL2012DP Receive alerts
The GTL2012 is a 2-bit translating transceiver designed for 3.3 V system interface with a GTL-/GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling receiver or as an LVTTL-to-GTL interface.
The GTL2012 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or 5 V CMOS inputs.
TSSOP8
Product Details
Features
- Operates as a 2-bit GTL-/GTL/GTL+ sampling receiver or as an LVTTL to GTL-/GTL/GTL+ driver
- 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
- GTL input and output 3.6 V tolerant
- Vref adjustable from 0.5 V to 0.5VCC
- Partial power-down permitted
- Latch-up protection exceeds 500 mA per JESD78
- ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-CC101
- Package offered: TSSOP8 (MSOP8) and VSSOP8
Documentation
Quick reference to our documentation types.
1-5 of 6 documents
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Data Sheet
2-bit LVTTL to GTL transceiver
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Application Note
AN10216
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Training Presentation
design_con_2003_tecforum_i2c_b_1
Design Resources
Hardware
2 hardware offerings
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Evaluation and Development BoardsSurface Mount to DIP Evaluation Board
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Evaluation and Development BoardsDual Synchronous Rectifier Evaluation Board