Design Files
1 design file
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Symbols and Footprints
GTL2018PW-TSSOP24-CAD Symbol and PCB Footprint – BXL File
8-Bit LVTTL-to-GTL Transceiver
GTL2018PW Receive alerts
The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL-/GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling receiver or as an LVTTL-to-GTL interface.
The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL or 5 V CMOS inputs.
Outline 3d SOT355-1
Product Details
Features
- Operates as an octal GTL-/GTL/GTL+ sampling receiver or as an LVTTL to GTL-/GTL/GTL+ driver
- 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
- GTL input and output 3.6 V tolerant
- Vref adjustable from 0.5 V to 0.5VCC
- Partial power-down permitted
- Latch-up protection exceeds 100 mA per JESD78
- ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-CC101
- AEC-Q100 compliance available
- Package offered: TSSOP24
Documentation
Quick reference to our documentation types.
1-5 of 7 documents
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Data Sheet
8-bit LVTTL to GTL transceiver
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Application Note
AN10216
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Package Information
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
