GTL2018PW: 8-bit LVTTL to GTL transceiver

Overview

The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL-/GTL/GTL+ bus.

The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling receiver or as an LVTTL-to-GTL interface.

The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL or 5 V CMOS inputs.

Operates as an octal GTL-/GTL/GTL+ sampling receiver or as an LVTTL to GTL-/GTL/GTL+ driver
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
GTL input and output 3.6 V tolerant
V_ref adjustable from 0.5 V to 0.5V_CC
Partial power-down permitted
Latch-up protection exceeds 100 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-CC101
AEC-Q100 compliance available
Package offered: TSSOP24

Operates as an octal GTL-/GTL/GTL+ sampling receiver or as an LVTTL to GTL-/GTL/GTL+ driver
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
GTL input and output 3.6 V tolerant
V_ref adjustable from 0.5 V to 0.5V_CC
Partial power-down permitted
Latch-up protection exceeds 100 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-CC101
AEC-Q100 compliance available
Package offered: TSSOP24