8-Bit LVTTL-to-GTL Transceiver


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Block Diagram

GTL2018 Block Diagram

GTL2018 Block Diagram


  • Operates as an octal GTL-/GTL/GTL+ sampling receiver or as an LVTTL to GTL-/GTL/GTL+ driver
  • 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
  • GTL input and output 3.6 V tolerant
  • Vref adjustable from 0.5 V to 0.5VCC
  • Partial power-down permitted
  • Latch-up protection exceeds 100 mA per JESD78
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-CC101
  • AEC-Q100 compliance available
  • Package offered: TSSOP24


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Design Files

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  • Symbols and Footprints

    GTL2018PW-TSSOP24-CAD Symbol and PCB Footprint – BXL File


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