NXP REFERENCE DESIGN LIBRARY
Technical content and expertise to help jump start your design and get you to production faster.
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LPC Cortex-M MCUs
- LPC5500 Cortex-M33
- LPC54000 Cortex-M4
- LPC1100 Cortex-M0+/M0
- LPC800 Series Cortex-M0+ MCUs
- LPC1200 Cortex-M0
- LPC1300 Cortex-M3
- LPC1500 Cortex-M3
- LPC1700 Cortex-M3
- LPC1800 Cortex-M3
- LPC4000 Cortex-M4
- LPC4300 Cortex-M4/M0
- LPC2000 Arm7 MCUs
- LPC3000 Arm9 MPUs
- Developer Resources
- LPC51U68
- Cyclone
- Cyclone FX
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LPC1800 Cortex-M3
- LPC1810FBD144
- LPC1810FET100
- LPC1812JBD144
- LPC1812JET100
- LPC1813JBD144
- LPC1813JET100
- LPC1815JBD144
- LPC1815JET100
- LPC1817JBD144
- LPC1817JET100
- LPC1820FBD144
- LPC1820FET100
- LPC1822JBD144
- LPC1822JET100
- LPC1823JBD144
- LPC1823JET100
- LPC1825JBD144
- LPC1825JET100
- LPC1827JBD144
- LPC1827JET100
- LPC1830FBD144
- LPC1830FET100
- LPC1830FET180
- LPC1830FET256
- LPC1833FET256
- LPC1833JBD144
- LPC1833JET100
- LPC1833JET256
- LPC1837FET256
- LPC1837JBD144
- LPC1837JET100
- LPC1837JET256
- LPC1850FET180
- LPC1850FET256
- LPC1853FET256
- LPC1853JBD208
- LPC1853JET256
- LPC1857FET256
- LPC1857JBD208
- LPC1857JET256
- LPC18S10FBD144
- LPC18S10FET100
- LPC18S30FBD144
- LPC18S30FET100
- LPC18S30FET256
- LPC18S37JBD144
- LPC18S37JET100
- LPC18S50FET180
- LPC18S50FET256
- LPC18S57JBD208
- LPC18S57JET256
- LPC18S50FET180
Overview
The LPC18S50FET180 is a Arm Cortex-M3 based microcontroller with security features for embedded applications. The Arm Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
The LPC18S50FET180 operates at CPU frequencies of up to 180 MHz. The Arm Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The Arm Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The LPC18S50FET180 includes 200 kB of on-chip SRAM, security features with AES engine, a quad SPI Flash Interface (SPIFI), a State Configurable Timer/PWM (SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.
Features
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Processor core
- Arm Cortex-M3 processor, running at frequencies of up to 180 MHz.
- Arm Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
- Arm Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
- Non-maskable Interrupt (NMI) input.
- JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
- Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
- System tick timer.
- On-chip memory
- 200 kB SRAM for code and data use.
- Multiple SRAM blocks with separate bus access.
- 64 kB ROM containing boot code and on-chip software drivers.
- 64 bit One-Time Programmable (OTP) memory for general-purpose use.
- Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key storage One bank can store an encrypted key for decoding the boot image.
- AES engine for encryption and decryption of the boot image and data with DMA support and programmable via a ROM-based API.
- Clock generation unit
- Crystal oscillator with an operating range of 1 MHz to 25 MHz.
- 12 MHz internal RC oscillator trimmed to 1.5 % accuracy over temperature and voltage.
- Ultra-low power RTC crystal oscillator.
- Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.
- Clock output.
- Configurable digital peripherals:
- State Configurable Timer (SCTimer/PWM) subsystem on AHB.
- Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like timers, SCTimer/PWM, and ADC0/1.
- Serial interfaces
- Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second.
- 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).
- One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY (USB0).
- One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to an external high-speed PHY (USB1).
- USB interface electrical test software included in ROM USB stack.
- Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification.
- Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge.
- Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.
- One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.
- One standard I²C-bus interface with monitor mode and standard I/O pins.
- Two I²S interfaces with DMA support, each with one input and one output.
- Digital peripherals
- External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.
- LCD controller with DMA support and a programmable display resolution of up to 1024 H x 768 V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping.
- Secure Digital Input Output (SD/MMC) card interface.
- Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves.
- Up to 118 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors.
- GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
- Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.
- Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
- Four general-purpose timer/counters with capture and match capabilities.
- One motor control PWM for three-phase motor control.
- One Quadrature Encoder Interface (QEI).
- Repetitive Interrupt timer (RI timer).
- Windowed watchdog timer.
- Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.
- Alarm timer; can be battery powered.
- Analog peripherals
- One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
- Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight input channels per ADC.
- Unique ID for each device.
- Power
- Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain.
- RTC power domain can be powered separately by a 3 V battery supply.
- Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
- Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.
- Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.
- Brownout detect with four separate thresholds for interrupt and forced reset.
- Power-On Reset (POR).
- Available as TFBGA180 package.
Target Applications
- Communication hubs
- Automotive aftermarket
- Power management
- Consumer health devices
- Embedded audio applications
- Industrial control
- Industrial automation
- White goods
Features
-
Processor core
- Arm Cortex-M3 processor, running at frequencies of up to 180 MHz.
- Arm Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
- Arm Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
- Non-maskable Interrupt (NMI) input.
- JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
- Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
- System tick timer.
- On-chip memory
- 200 kB SRAM for code and data use.
- Multiple SRAM blocks with separate bus access.
- 64 kB ROM containing boot code and on-chip software drivers.
- 64 bit One-Time Programmable (OTP) memory for general-purpose use.
- Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key storage One bank can store an encrypted key for decoding the boot image.
- AES engine for encryption and decryption of the boot image and data with DMA support and programmable via a ROM-based API.
- Clock generation unit
- Crystal oscillator with an operating range of 1 MHz to 25 MHz.
- 12 MHz internal RC oscillator trimmed to 1.5 % accuracy over temperature and voltage.
- Ultra-low power RTC crystal oscillator.
- Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.
- Clock output.
- Configurable digital peripherals:
- State Configurable Timer (SCTimer/PWM) subsystem on AHB.
- Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like timers, SCTimer/PWM, and ADC0/1.
- Serial interfaces
- Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second.
- 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).
- One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY (USB0).
- One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to an external high-speed PHY (USB1).
- USB interface electrical test software included in ROM USB stack.
- Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification.
- Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge.
- Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.
- One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.
- One standard I²C-bus interface with monitor mode and standard I/O pins.
- Two I²S interfaces with DMA support, each with one input and one output.
- Digital peripherals
- External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.
- LCD controller with DMA support and a programmable display resolution of up to 1024 H x 768 V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping.
- Secure Digital Input Output (SD/MMC) card interface.
- Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves.
- Up to 118 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors.
- GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
- Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.
- Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
- Four general-purpose timer/counters with capture and match capabilities.
- One motor control PWM for three-phase motor control.
- One Quadrature Encoder Interface (QEI).
- Repetitive Interrupt timer (RI timer).
- Windowed watchdog timer.
- Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.
- Alarm timer; can be battery powered.
- Analog peripherals
- One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
- Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight input channels per ADC.
- Unique ID for each device.
- Power
- Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain.
- RTC power domain can be powered separately by a 3 V battery supply.
- Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
- Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.
- Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.
- Brownout detect with four separate thresholds for interrupt and forced reset.
- Power-On Reset (POR).
- Available as TFBGA180 package.
Target Applications
- Communication hubs
- Automotive aftermarket
- Power management
- Consumer health devices
- Embedded audio applications
- Industrial control
- Industrial automation
- White goods
