Kinetis K30-72 MHz, Mixed-Signal Integration Microcontrollers (MCUs) based on Arm® Cortex®-M4 Core

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Block Diagram

Kinetis K30 Mid-Performance Segment LCD MCUs Block Diagram

Kinetis K30 Mid-Performance Segment LCD MCUs Block Diagram

Features

Ultra-Low-Power

  • 10 low-power modes with power and clock gating for optimal peripheral activity and recovery times. Stop currents of <1.45 µA, run currents of <277 µA/MHz, 4 µs wake-up from Stop mode
  • Full memory and analog operation down to 1.71V for extended battery life
  • Low-leakage wake-up unit with up to eight internal modules and sixteen pins as wake-up sources in low-leakage stop (LLS)/very low-leakage stop (VLLS) modes
  • Low-power timer for continual system operation in reduced power state

Flash, SRAM and FlexMemory

  • 64-256 KB flash. Fast access, high reliability with 4-level security protection
  • 16-64 KB of SRAM
  • FlexMemory: 2KB of user-segmentable byte write/erase EEPROM for data tables/system data. EEPROM with over 10M cycles and flash with 70 µsec write time (brownouts without data loss or corruption). No user or system intervention to complete programming and erase functions and full operation down to 1.71V. In addition, 32KB FlexNVM for extra program code, data or EEPROM backup

Mixed-Signal capability

  • Up to two high-speed 16-bit ADCs with configurable resolution. Single or differential output mode operation for improved noise rejection. 500 ns conversion time achievable with programmable delay block triggering
  • One 12-bit DAC for analog waveform generation for audio applications
  • Three high-speed comparators providing fast and accurate motor over-current protection by driving PWMs to a safe state
  • Two programmable gain amplifiers with x64 gain for small amplitude signal conversion
  • Analog voltage reference provides an accurate reference to analog blocks, ADC and DAC, and replaces external voltage references to reduce system cost

Performance

  • Cortex-M4 core + DSP
  • 72 MHz, single cycle MAC, single instruction multiple data (SIMD) extensions
  • 16-channel DMA for peripheral and memory servicing with reduced CPU loading and faster system throughput
  • Cross bar switch enables concurrent multi-leader bus accesses, increasing bus bandwidth
  • Independent flash banks allow concurrent code execution and firmware updating with no performance degradation or complex coding routines

Timing and Control

  • FlexTimer with a total of 8 channels. Hardware dead-time insertion and quadrature decoding for motor control
  • Carrier modulator timer for infrared waveform generation in remote control applications
  • Four-channel 32-bit periodic interrupt timer provides time base for RTOS task scheduler or trigger source for ADC conversion and programmable delay block

Human-Machine Interface

  • Hardware touch-sensing interface with up to 16 inputs. Operates in all low power modes (minimum current adder when enabled). Hardware implementation avoids software polling method. High sensitivity level allows use of overlay surfaces upto 5 mm thick
  • Flexible, low-power LCD controller with up to 288 segments (36x8 or 40x4). LCD blink mode enables low average power while remaining in low-power mode. Segment fail detect guards against erroneous readouts and reduces LCD test costs. Frontplane/backplane reassignment provides pin-out flexibility easing PCB design and allows LCD configuration changes via firmware with no hardware re-work. Supports multiple 3V and 5V LCD panel sizes with fewer segments (pins) than competitive controllers and no external components. Unused LCD pins can be configured as other GPIO functions

Connectivity and Communications

  • Up to 5 UARTs with IrDA support including one UART with ISO7816 smart card support. Variety of data size, format and transmission/reception settings supported for multiple industrial communication protocols
  • Inter-IC Sound (I2S) serial interface for audio system interfacing
  • One CAN module for industrial network bridging
  • Up to two DSPI and two I2C

Reliability, Safety and Security

  • Cyclic redundancy check engine validates memory contents and communication data, increasing system reliability
  • Independent-clocked COP guards against clock skew or code runaway for fail-safe applications such as the IEC 60730 safety standard for household appliances
  • External watchdog monitor drives output pin to safe state external components if watchdog event occurs
  • This product is included in NXP's product longevity program, with assured supply for a minimum of 10 years after launch

External Peripheral Supports

  • FlexBus external bus interface provides interface options to memories and peripherals such as graphics displays. Supports up to 6 chip selects and 2GB addressable space

Documentation

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Design Resources

Design Files

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Hardware

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Software

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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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To find a complete list of our partners that support this product, please see our Partner Marketplace.

Training

4 trainings