Scalable Entry Level 32-bit Microcontroller (MCU) based on Arm® Cortex®-M0 Cores

LPC11D00

Product Details

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Features

System

  • Cortex-M0 processor, running at frequencies of up to 50 MHz
  • Cortex-M0 built-in nested vectored interrupt controller (NVIC)
  • Serial Wire Debug
  • System tick timer

LCD Driver

  • 40 segments
  • One to four backplanes
  • On-chip display Ram with auto-increment addressing

Memory

  • 32 KB on-chip flash programming memory
  • 8 KB SRAM
  • In-System programming (ISP) and In-Application programming (IAP) via on-chip bootloader software

Digital peripherals

  • Up to 42 General purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. In addition, a configurable open-drain mode is supported
  • GPIO pins can be used as edge and level sensitive interrupt sources
  • High-current output driver (20 mA) on one pin
  • High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus
  • Four general purpose counter/timers with up to eight capture inputs and up to 13 match outputs
  • Programmable windowed watchdog timer (WDT)

Analog peripherals

  • 10-bit ADC with input multiplexing among 8 pins

Serial interfaces

  • UART with fractional baud rate generation, internal FIFO, and RS-485 support
  • Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities
  • I²C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode

Clock generation

  • 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock
  • Crystal oscillator with an operating range of 1 MHz to 25 MHz
  • Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz
  • PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator
  • Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock

Power control

  • Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes
  • Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call
  • Three reduced power modes: Sleep, Deep-sleep, and Deep power-down
  • Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins
  • Power-On Reset (POR)
  • Brownout detect with up to four separate thresholds for interrupt and forced reset

Additional features

  • Unique device serial number for identification
  • Single power supply (1.8 V to 3.6 V)
  • Available in LQFP100 package

Design Resources

Documentation

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Design Files

1 design file

Hardware

5 hardware offerings

Software

1 software file

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

4 engineering services

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Training

2 trainings

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