Scalable, Entry-Level 32-bit Microcontrollers (MCUs)

LPC11AXX

Product Details

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Features

System

  • Arm Cortex-M0 or Arm Cortex-M0+ processor, running at frequencies of up to 50 MHz
  • Arm Cortex-M0 or Arm Cortex-M0+ built-in nested vectored interrupt controller (NVIC)
  • Serial wire debug (SWD) and JTAG boundary scan modes supported
  • System tick timer

Memory

  • Up to 32 KB on-chip flash programming memory
  • Up to 4 KB on-chip EEPROM data memory; byte erasable and byte programmable
  • Up to 8 KB SRAM data memory
  • 16 KB boot ROM
  • In-System programming (ISP) and In-application programming (IAP) for flash and EEPROM via on-chip bootloader software
  • Includes ROM-based 32-bit integer division and I2C-bus driver routines

Digital peripherals

  • Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode
  • Up to 16 pins are configurable with a digital input glitch filter for removing glitches with widths of 10ns or less and two pins are configurable for 50ns glitch filters
  • GPIO pins can be used as edge and level sensitive interrupt sources
  • High-current output driver (20 mA) on one pin
  • High-current sink drivers (20 mA) on two open-drain pins
  • Four general purpose counter/timers with a total of 16 capture inputs and 14 match outputs.
  • Programmable windowed watchdog timer (WWDT) with a dedicated, internal low-power watchdog oscillator (WDOsc)

Analog peripherals

  • 10-bit ADC with input multiplexing among 8 pins
  • 10-bit DAC with flexible conversion triggering
  • Highly flexible analog comparator with a programmable voltage reference
  • Integrated temperature sensor
  • Internal voltage reference
  • Undervoltage lockout (UVLO) protection against power-supply droop below 2.4V

Serial interfaces

  • USART with fractional baud rate generation, internal FIFO, and support for RS-485/9-bi mode and synchronous mode
  • Two SSP controllers with FIFO and multi-protocol capabilities. Support data rates of up to 25 Mbit/s
  • I2C-bus interface supporting the full I2C-bus specification and fast-mode plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode

Clock generation

  • Crystal oscillator with an operating range of 1 MHz to 25 MHz
  • 12 MHz internal RC oscillator (IRC) trimmed to 1 % accuracy that can optionally be used as a system clock
  • Internal low-power, low-frequency oscillator (LFOsc) with programmable frequency output
  • Clock input for external system clock (25 MHz typical)
  • PLL allows CPU operation up to the maximum CPU rate with the IRC, the external clock or the SysOsc as clock sources
  • Clock output function with divider that can reflect the SysOsc, IRC, the main clock, or the LFOsc

Power control

  • Supports on reduced power mode: the Arm Sleep mode
  • Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call
  • Processor wake-up from reduced power mode using any interrupt
  • Power-on reset (POR).
  • Brownout detect (BOD) with two programmable thresholds for interrupt and one hardware controlled reset trip point
  • POR and BOD are always enabled for rapid UVLO protection against power supply voltage droop below 2.4

Additional features

  • Unique device serial number for identification
  • Single 3.3 V power supply (2.6 V to 3.6 V)
  • Available as LQFP48, HVQFN33, and WLCSP20 packages

Design Resources

Documentation

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Software

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Engineering Services

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Training

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