The LPC18S50FET256 is a Arm Cortex-M3 based microcontroller with security
features for embedded applications. The Arm Cortex-M3 is a next generation core that
offers system enhancements such as low power consumption, enhanced debug features,
and a high level of support block integration.
The LPC18S50FET256 operates at CPU frequencies of up to 180 MHz. The Arm Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The Arm Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
The LPC18S50FET256 includes 200 kB of on-chip SRAM, security features with
AES engine, a quad SPI Flash Interface (SPIFI), a State Configurable Timer/PWM
(SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external
memory controller, and multiple digital and analog peripherals.