Multimedia Applications Processors - Automotive Infotainment, High Resolution, High Color Display, High Performance, Low Power,  Arm9™ Core

Product Details

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Block Diagram

i.MX255 Multimedia Applications Processor Block Diagram

i.MX255 Multimedia Applications Processor Block Diagram

Features

CPU Complex

  • Arm926EJ-S™
  • 400 MHz maximum speed
  • 128 KB Integrated SRAM
  • 16 KB I/D L1 Cache

Multimedia

  • Security Engine
  • LCD Controller
  • Resistive Touchscreen Controller
  • CMOS Sensor Interface

Connectivity

  • External memory interface: DDR2, mDDR, SDRAM, mSDRAM, NOR, SLC/MLC NAND
  • 10/100 Ethernet MAC
  • 2 x FlexCan Controllers/li>
  • 480Mbps USB 2.0 OTG + PHY
  • 480Mbps USB 2.0 Host + PHY
  • 5 x UART, 3 x CSPI, 3 x I2C, 2 x SSI/I2S, ESAI
  • 2 x MMC+/SD/SDIO
  • 2 x Smartcard Interfaces
  • PATA/CE-ATA
  • 3 x12-bit ADC
  • 3.3V General Purpose I/O

Technology

  • 0.8mm MAPBGA 400-pin package
  • -40 to +85C

Product Longevity

Design Resources

Documentation

Quick reference to our documentation types.

1-5 of 23 documents

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Design Files

1 design file

Hardware

2 hardware offerings

Software

3 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 28 engineering services

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To find a complete list of our partners that support this product, please see our Partner Marketplace.

Training

2 trainings

Support

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