Layerscape® Access LA9310 Programmable Baseband Processor

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Product Details

Block Diagram

Layerscape Access LA9310 Block Diagram

Layerscape Access LA9310 Block Diagram

Features

Core and Memory Complex

  • One VSPA generation 2, 16AU DSP at up to 614MHz (~80 GFLOP)
  • One M4 32b Arm® core at up to 307MHz

Connectivity and I/O

  • One PCIe Gen3 lane
  • Five {I+Q} ADCs, each sampling at up to 153M samples per second
  • One {I+Q} DAC, sampling at up to 153M samples per second

Acceleration

  • Forward error correction for proprietary communication protocols
  • DMA for internal and host side data movement

Low speed I/O and RFIC control

  • General purpose single lane SPI with four Chip Selects
  • Lightweight LVDS Communication Protocol for RFIC Interface
  • I2C controller
  • UART
  • JTAG

Device

  • 8mm x 8mm package
  • 1.5W total max power at 105C

Part numbers include: LA9310S7S11AA, LA9310X7S11AA.

Documentation

Quick reference to our documentation types.

5 documents

Design Resources

Hardware

1 hardware offering

Software

1 software file

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 8 engineering services

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