32-bit MCU for Automotive Powertrain and Industrial Applications

MPC5565

Designed for engine management and high temperature industrial environments, the NXP® MPC5565 embedded controller targets mid-range applications and use cases requiring complex, real-time control.

  • Helps increase fuel efficiency and improved emissions
  • Offers system performance of up to five times that of its MPC500 predecessors
  • Enables easy migration to next-generation 3 MB flash-embedded controllers
  • Facilitates reuse of legacy software architectures
  • Pin-and code-compatible with other MPC5500 family MCUs
  • Includes comprehensive development tools to help simplify and speed system design

Product Details

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Block Diagram

MPC5565 Block Diagram

MPC5565 Block Diagram
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Features

Our e200z6 Core

  • High-performance 132 MHz 32-bit Power Architecture technology core with VLE
  • Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
  • SPE (signal processing extension): DSP, SIMD and floating point capabilities

Memory

  • 2 MB of embedded flash memory with error correction coding (ECC) and read while write capability (RWW)
  • 64 KB on-chip static RAM with error correction coding (ECC)
  • 8 KB of cache (with line-locking) that can be configured as additional RAM

System

  • An enhanced time processor unit (eTPUs), each with 32 I/O channels and 14K of dedicated SRAM
  • 32-channel eDMA (enhanced direct memory access) controller
  • Interrupt controller (INTC) capable of handling 339 selectable-priority interrupt sources
  • Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
  • MPC500 compatible 32-bit external bus interface
  • Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities > 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
  • 324-pin PBGA package
  • Temperature range: -40 to 125ºC

I/O

  • 40-channel dual enhanced queued analog-to-digital converters (eQADC)—each up to 12-bit resolution and up to 1.25 us conversions, six queues with triggering and DMA support
  • Three deserial serial peripheral interface (DSPI) modules—16-bits wide up to six chip selects each
  • Three controller area network (CAN) modules with 64 buffers each
  • Two enhanced serial communication interface (eSCI) modules
  • 24-channel enhanced multiple I/O system (EMIOS) with unified channels

Included in NXP product longevity program

Key Parametrics

  • Flash (kB)
    2000
  • Operating Frequency [Max] (MHz)
    132
  • GPIO
    192

Design Resources

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Documentation

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Software

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Note: For better experience, software downloads are recommended on desktop.

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Training

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