QorIQ® P1024/15 Single- and Dual-Core Communications Processors

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Block Diagram

Freescale QorIQ P1024/15 Communication Processor Block Diagram

QorIQ<sup>&#174;</sup> P1024/15 Communication Processor Block Diagram

Features

Core Complex

  • Dual (P1024) or single (P1015) high-performance Power Architecture® e500 cores, 32 KB L1 cache, up to 667 MHz
  • 256 KB L2 cache with ECC, also configurable as SRAM and stashing memory

Networking Elements

  • Three 10/100/1000 Mbps enhanced triple speed Ethernet controllers (eTSEC)
  • Two SGMII interfaces
  • Support for IEEE® 1588

Accelerators and Memory Control

  • DDR3 32-bit memory controller with ECC support
  • Integrated security engine
    • Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi
    • XOR acceleration

Basic Peripherals and Interconnect

  • Four lane SERDES up to 3.125 GHz multiplexed across controllers
  • Two PCI Express® Gen1.0 interface controllers
  • Two USB2.0 controllers
  • Enhanced Local Bus Controller (eLBC)
  • TDM
  • eSDHC
  • Dual I²C, DUART, PIC, DMA, GPIO

Additional Features

Design Resources

Documentation

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Hardware

2 hardware offerings

Software

3 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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