QorIQ® P2020 and P2010 Dual- and Single-Core Communications Processors

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  • This page contains information on a product that is not recommended for new designs.

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Product Details

Block Diagram

Freescale QorIQ P2020/10 Communication Processor Block Diagram

Freescale QorIQ P2020/10 Communication Processor Block Diagram

Features

Core Complex

  • Dual (P2020) or single (P2010) high-performance Power Architecture® e500 cores
  • Up to 1.33 GHz
  • 32 KB L1 and 512KB L2 caches

Networking Elements

  • Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
  • Four SerDes up to 3.125 GHz multiplexed across controllers supporting:
    • Two PCI Express® interfaces
    • Two Serial RapidIO® interfaces
    • Two SGMII interfaces

Accelerators and Memory Control

  • Integrated security engine
  • Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi, XOR acceleration

Basic Peripherals and Interconnect

  • Dual high-speed USB controllers (USB 2.0)
  • eLBC, eSDHC, Dual I²C, DUART, PIC, DMA, GPIO

Additional Features

  • Package: 689-pin temperature-enhanced plastic BGA (TEPBGA2)
  • 0C to 125C Tj -40C to 125C Tj option

Comparison Table

P2010 P2020
Cores 1 2
Core Frequency 800 - 1200 MHz 800 - 1200 MHz
L2 Cache 512KB 512KB
DDR 32/64-bit DDR2/DDR3 32/64-bit DDR2/DDR3
GbE 3 x 10/100/1000 3 x 10/100/1000
PCIe Gen 1.0 3 controllers w/ 4 SERDES 3 controllers w/ 4 SERDES
sRIO 1.2 2 x1 or 1 x4 2 x1 or 1 x4
USB 2.0 1 1
Memory Card SD/MMC SD/MMC
Other interfaces SPI, 2xI2C, DUART SPI, 2xI2C, DUART
Accelerators SEC3.1 SEC3.1

Design Resources

Documentation

Quick reference to our documentation types.

1-5 of 52 documents

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Design Files

1 design file

Hardware

4 hardware offerings

Software

4 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 29 engineering services

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Training

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