S32R Radar MCU – High Performance for High Resolution Radar

S32R41

S32R41 is a radar microprocessor unit (MPU) dedicated to advanced 77GHz radar applications. The architecture features Arm® Cortex®-A53 and Cortex-M7 cores which are combined with radar processing accelerators (SPT and BBE) to create an optimal radar processing chain. It is designed to target the ADAS radar market, and is also suitable for industrial and consumer radar applications.

The comprehensive feature set enables the S32R41 family to span the radar application space. The high performance processing in combination with Dual MIPI CSI interfaces and 8MB of local SRAM enable 4D high resolution radar systems. The S32R41 also matches advanced corner and long range front radar applications.

The S32R41’s architecture is part of NXP’s scalable radar portfolio. The processor cores and radar accelerators are similar across the family. This creates a common software product catalog between the S32R41 4D high resolution radar processor and the S32R45 4D imaging radar processor. The S32R41 and S32R45 devices, when paired with the NXP TEF82xx 77GHz radar transceivers, provide scalable solutions for the developing high resolution and imaging radar market.

Product Details

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Block Diagram

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S32R41 Radar MCU Block Diagram

S32R41 Radar MCU Block Diagram

S32R41 Radar MCU App Block Diagram

S32R41 Radar MCU App Block Diagram
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Features

General

  • Cortex-A53 @800 MHz
  • 2 Cortex-M7 lockstep pairs @400 MHz
  • 8 MB SRAM with ECC
  • HSE security module
  • 1x SAR ADC 16-ch
  • 2x MIPI CSI2
  • 2x Ethernet interfaces, 1x RGMII (1000 Mbps), 1x RMII (100 Mbps)
  • 2x FlexCAN with FD
  • ISO26262 SEooC ASIL B(D)
  • -40 ºC to 150 °C (Tj) AEC-Q100 Grade-1

SPT 3.5 @600 MHz

  • BBE32 DSP @600MHz

SAF Software modules provided

  • Built-in Self-Test (BIST) manager covering both logic BIST (LBIST) and memory BIST (MBIST)
  • Extended microcontroller error manager (eMCEM)
  • Mode selector
  • Safety boot (sBoot)
  • Software recovery

Design Resources

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