Transport Barrier System
TRANSPORTBAR Receive alerts
From machine to control access, transport barrier systems can validate tickets and also take contactless payments from credit cards and mobile phones (requiring PCI-PTS 4.0 certification). These systems maintain a database of all transactions including a local copy kept in the machine and a copy uploaded to a central database.
Features
K81 Memory and Scalability
- 256 KB of Flash
- 256 KB of SRAM
- CPU cache consisting of separate 8 KB I/D and 8 KB system cache
- QSPI controller optimized for XIP from external serial NOR flash memories with support for quad and octal data interfaces
- SDRAM and external memory bus interfaces
- eMMC/SDIO interface through eSDHC peripheral
i.MX 6ULL CPU Complex & Display
- Cortex-A7 core up to 900 MHz, 128 KB L2 cache
- Parallel LCD Display up to WXGA (1366x768)
- 8/10/16/24-bit Parallel Camera Sensor Interface
- Electrophoretic display controller support direct-driver for E-Ink EPD panel, with up to 2048x1536 resolution at 106 Hz
Memory
- 16-bit LP-DDR2, DDR3/DDR3L
- 8/16-bit Parallel NOR FLASH / PSRAM
- Dual-channel Quad-SPI NOR FLASH
- 8-bit Raw NAND FLASH with 40-bit ECC
Connectivity
- 2x MMC 4.5/SD 3.0/SDIO Port
- 2x USB 2.0 OTG, HS/FS, Device or Host with PHY
- Audio Interfaces include 3x I2S/SAI, S/PDIF Tx/Rx
- 2x 10/100 Ethernet with IEEE 1588
- 2x 12-bit ADC, up to 10 input channel total, with resistive touch controller (4-wire/5-wire)