The JUNCAP model describes the behavior of the diodes that are formed by the source, drain, or well-to-bulk junctions in MOST devices. In order to include the effects from differences in the sidewall, bottom, and gate-edge-junction profiles, these three contributions are calculated separately in the JUNCAP model.
The files containing the level 1 and level 200 code are "device_juncap.c" and "device_juncap2.c" respectively. If you use the included solver, please make sure that you compile on a system that supports Fortran 77.
The source code for Juncap level 200 has been automatically generated from a Verilog-A description of the model.
The models are included in a dynamically loaded library called SiMKit. SiMKit is related to the following circuit simulators used within NXP:
The definition of the Juncap model Level 1 and level 200 are available in PDF format in the documentation tab.Juncap, level 1. This model describes
Juncap, level 200. This model is a major update of the JUNCAP level 1 model. It models all the effects already present in level 1, and has many new features:
The SiMKit C-code for Juncap level 200 has been automatically generated from a Verilog-A description of the model. The functionality of this SiMKit C-code is the same as that of the Verilog-A. The Verilog-A code of Juncap level 200 can be downloaded from the TU Delft PSP website.