PLDA : NXP Approved Engineering Consultants Partner


PLDA Training is a division of PLDA Group, a privately-owned technology group focused on delivering leading-edge products and services. PLDA Training provides more than 70 courses, providing 360° skills and expertise in System-on-Chip design, on topics ranging from CPUs to connectivity and network implementation. PLDA Training’s experienced trainers provide real-life case studies and ongoing support after training, enabling customers to drive their designs further. PLDA Training shares the PLDA Group’s goal of enabling manufacturers of electronic components and systems worldwide to design and market highly differentiated products faster, without risk, and with dedicated support from highly skilled engineering teams.

PLDA  Recommended Solutions

 
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NXP Partner Solutions Offered
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Offering Type Description Supported NXP Solutions
Live In-depth Training
NXP E300 Training This course provides an in-depth description of the e300 architecture Low level programming: assembler and C is explained through code examples The instruction pipeline is fully detailed to understand how to estimate worst case execution time
NXP E500 Training This course provides an in-depth description of the e500 architecture. Low level programming: assembler and C is explained through code examples. The instruction pipeline is fully detailed to understand how to estimate worst case execution time.
NXP E500MC Training In-depth description of the e500mc architecture. Low level programming, assembler and C, explained through code examples. Detail of the instruction pipeline to understand how to estimate worst case execution time. MESI cache coherency protocol.
NXP E5500 Training In-depth description of the e5500 architecture. 32-bit / 64-bit computation modes transitions. Low level programming, assembler and C, explained through code examples. Platform virtualization through the hypervisor privilege level.
NXP E6500 Training In-depth description of the e6500 architecture. 32-bit / 64-bit computation modes transitions Low level programming. MESI cache coherency protocol. Platform virtualization through the hypervisor privilege level.
NXP i.MX51 Training Software and hardware implementation of the i.MX51. Description of all I/O and memory interfaces: DDR2, WEIM, NAND Flash. Reset sequence and secure boot. Initializing the SDMA. Security features.
NXP i.MX6DL/i.MX6DP/i.MX6DQP Training Software and hardware implementation of the i.MX6DQP. Description of all I/O and memory interfaces: DDR3, EIM, GPMI and PCIe. Reset sequence and secure boot. Initializing the SDMA. Security features.
NXP i.MX6SL Training Software and hardware implementation of the i.MX6SL. Description of all I/O and memory interfaces: DDR3 and EIM. Reset sequence and secure boot. Initializing the SDMA. Security features.
NXP i.MX6SX Training Software and hardware implementation of the i.MX6SX. Description of all I/O and memory interfaces: DDR3, EIM, GPMI and PCIe. Reset sequence and secure boot. Initializing the SDMA. Security features.
NXP i.MX6UL Training Software and hardware implementation of the i.MX6UL. Description of all I/O and memory interfaces: DDR3, EIM and GPMI. Reset sequence and secure boot. Initializing the SDMA. Security features.
NXP i.MX7 Training Software and hardware implementation of the i.MX7. Description of all I/O and memory interfaces: DDR3, EIM, GPMI and PCIe. Reset sequence and secure boot. Initializing the SDMA. Security features.
NXP LS1021A Training Software and hardware implementation of the LS102X. Description of all I/O and memory interfaces: DDR4, IFC, QuadSPI and PCIe. Reset sequence and secure boot. Security features. Ethernet MACs with network accelerators.
NXP LS1043A Training Software and hardware implementation of the LS1043A. Description of all I/O and memory interfaces: DDR4, IFC, QuadSPI and PCIe. Reset sequence and secure boot. Security features. Detail of DPAA networks accelerators.
NXP LS2085A Training Software and hardware implementation of the LS2085A. Description of all I/O and memory interfaces: DDR4, IFC, QuadSPI and PCIe. Reset sequence and secure boot. Security features. Detail of DPAA2 networks accelerators.
NXP MPC7448 / E600 Training This course provides an in-depth description of the MPC7448 architecture. Low level programming: assembler and C is explained through code examples. The course explains how instructions and data navigate between SDRAM, L1 cache and L2 cache.
NXP MPC8323E Training This course handles the software and hardware implementation of the MPC8323. All I/O and memory interfaces are studied: DDR2, LBC and PCI. The hardware implementation, power supplies, clocking, PCB guidelines is studied.
NXP MPC8349E Training This course handles the software and hardware implementation of the MPC8439EAD All I/O and memory interfaces are studied: DDR2, LBC and PCI The hardware implementation, power supplies, clocking, PCB guidelines is studied
NXP MPC8536E Training This course handles the software and hardware implementation of the MPC8536E. Sequences are explaining how data and instructions navigate between L1 caches, L2 cache and memory and also highlights the benefits of stashing.
NXP MPC8548E Training This course handles the software and hardware implementation of the MPC8548E. Sequences are explaining how data and instructions navigate between L1 caches, L2 cache and memory and also highlights the benefits of stashing.
NXP MPC8572E Training This course handles the software and hardware implementation of the MPC8572E. Sequences are explaining how data and instructions navigate between L1 caches, L2 cache and memory and also highlights the benefits of stashing.
NXP MPC8610 Training This course handles the software and hardware implementation of the MPC8610. All I/O and memory interfaces are studied: DDR2, LBC and PCIe. The reset sequence is detailed.
NXP MPC8641D Training This course handles the software and hardware implementation of the MPC8641D. All I/O and memory interfaces are studied: DDR2, LBC, PCIe and SRIO. The reset sequence is detailed.
NXP MULTICORE SOC FOR SAFETY CRITICAL SYSTEMS Training This course has been designed for companies developing safety critical equipments based on NXP multicore SoCs. After having defined the important multicore concepts, it details how they are implemented in both PowerPC QorIQs and ARM LayerScape SoCs.
NXP P1010 Training This course handles the software and hardware implementation of the P1010. All I/O and memory interfaces are studied: DDR3, IFC and PCIe. The reset sequence is detailed and also the secure boot sequence.
NXP P1021 Training This course handles the software and hardware implementation of the P1021. All I/O and memory interfaces are studied: DDR3, eLBC and PCIe. The reset sequence is detailed.
NXP P1022 Training This course handles the software and hardware implementation of the P1022. All I/O and memory interfaces are studied: DDR3, eLBC and PCIe. The reset sequence is detailed.
NXP P2020 Training This course handles the software and hardware implementation of the P2020. All I/O and memory interfaces are studied: DDR3, eLBC and PCIe. The reset sequence is detailed.
NXP P2041 Training Software and hardware implementation of the P2041. Description of all I/O and memory interfaces: DDR3, eLBC, SRIO and PCIe. Reset sequence and secure boot. Detail of DPAA networks accelerators.
NXP P3041 Training Software and hardware implementation of the P3041. Description of all I/O and memory interfaces: DDR3, eLBC, SRIO and PCIe. Reset sequence and secure boot. Detail of DPAA networks accelerators.
NXP P4080 Training Software and hardware implementation of the P4080. Description of all I/O and memory interfaces: DDR3, eLBC, SRIO and PCIe. Reset sequence and secure boot. Detail of DPAA networks accelerators.
NXP P5020 Training Software and hardware implementation of the P5020. Description of all I/O and memory interfaces: DDR3, eLBC, SRIO and PCIe. Reset sequence and secure boot. Detail of DPAA networks accelerators.
NXP P5040 Training Software and hardware implementation of the P5040. Description of all I/O and memory interfaces: DDR3, eLBC, SRIO and PCIe. Reset sequence and secure boot. Detail of DPAA networks accelerators.
NXP Qorivva E200Z0 Training This course provides an in-depth description of the e200z0 architecture. Low level programming: assembler and C is explained through code examples. The instruction pipeline is fully detailed to understand how to estimate worst case execution time.
NXP Qorivva E200Z3 Training This course provides an in-depth description of the e200z3 architecture. Low level programming: assembler and C is explained through code examples. The instruction pipeline is fully detailed to understand how to estimate worst case execution time.
NXP Qorivva E200Z4 Training This course provides an in-depth description of the e200z4 architecture. Low level programming: assembler and C is explained through code examples. The instruction pipeline is fully detailed to understand how to estimate worst case execution time.
NXP Qorivva E200Z7 Training This course provides an in-depth description of the e200z7 architecture. Low level programming: assembler and C is explained through code examples. The instruction pipeline is fully detailed to understand how to estimate worst case execution time.
NXP Qorivva MPC5748G Training Explaining the architecture of this SoC. Providing all information for board designers. Detailing the safety mechanisms. Describing the interrupt management. Studying the operation of all peripherals.
NXP Qorivva MPC5777M Training Explaining the architecture of this SoC. Providing all information for board designers. Detailing the safety mechanisms. Describing the interrupt management. Studying the operation of all peripherals.
NXP T1024 Training Software and hardware implementation of the T1024. Description of all I/O and memory interfaces: DDR4, IFC and PCIe. Reset sequence and secure boot. Detail of DPAA networks accelerators.
NXP T1040 Training Software and hardware implementation of the T1040. Description of all I/O and memory interfaces: DDR4, IFC and PCIe. Reset sequence and secure boot. Detail of DPAA networks accelerators. Detail of integrated Ethernet switch.
NXP T2080 Training Software and hardware implementation of the T2080. Description of all I/O and memory interfaces: DDR3, IFC, SRIO and PCIe. Reset sequence and secure boot. Detail of DPAA networks accelerators.
NXP T4240 Training Software and hardware implementation of the T4240. Description of all I/O and memory interfaces: DDR3, IFC, SRIO and PCIe. Reset sequence and secure boot. Detail of DPAA networks accelerators.

Company Information


Company Headquarters
805 Rue Jean René Guillibert Gauthier de la Lauzière
Aix en Provence,PACA
13290
France
www.pldatraining.com/
+33428380465
Primary Contact
Sonia  Erceau
serceau@plda.com
Member Since
August 2016


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