The PRH601 is an integrated RF Identification reader module for contactless communication at 13.56 MHz and 125 kHz. It implements an additional 32-bit ARM CortexM0 microcontroller core.
The package contains three dies:
Not all pins of the LPC1227 specified in the datasheet are available at the reader module.
The devices does not implement any interconnection inside the package. This enables access to all signals during system development. The device can be replaced by a integrated reader module PRH601 if no 125 kHz functionality is required. A re-design of the PCB is not required in this case.
The HITAG Reader Chip HTRC110 is intended for use with transponders, which are based on the HITAG silicon (HT1ICS3002x or HT2ICS2002x). In addition the IC supports other 125 kHz transponder types using amplitude modulation for the write operation and AM/PM for the read operation. The receiver parameters (gain factors, filter cutoff frequencies) can be optimized to system and transponder requirements.
The HTRC110 is designed for easy integration into RF-identification readers. State-of-the-art technology allows almost complete integration of the necessary building blocks. A powerful antenna driver/modulator together with a low-noise adaptive sampling time demodulator, programmable filters/amplifier and digitizer build the complete transceiver unit, required to design high-performance readers. A three-pin microcontroller interface is employed for programming the HTRC110 as well as for the bidirectional communication with the transponders. The three-wire interface can be changed into a two-wire interface by connecting the data input and the data output. Tolerance dependent zero amplitude modulation caused severe problems in envelope detector systems, resulting in the need of very low tolerance reader antennas. These problems are solved by the new Adaptive Sampling Time technique (AST).
The CLRC663 is a highly integrated transceiver IC for contactless communication at 13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz.
The CLRC663 transceiver ICs support following different operating modes:
The CLRC663 internal transmitter is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/MIFARE cards and transponders without additional active circuitry. The receiver module provides a robust and efficient implementation for demodulation and decoding signals from ISO 14443A/MIFARE compatible cards and transponders. The digital module manages the complete ISO 14443A framing and error detection (parity and CRC) functionality.The CLRC663 supports MIFARE 1K, MIFARE 4K, MIFARE Ultralight®, MIFARE®, Ultralight C, MIFARE PLUS and MIFARE DESFire products. The CLRC663 supports contactless communication and uses MIFARE higher transfer speeds up to 848 kBd in both directions.
The CLRC663 supports all layers of the ISO/IEC 14443B reader/writer communication scheme, given correct implementation of additional components, like oscillator, power supply, coil etc. and provided that standardised protocols, e.g. like ISO/IEC 14443-4 and/or ISO/IEC 14443B anticollision are correctly implemented.
Enabled in Reader/Writer mode for FeliCa, the CLRC663 transceiver IC supports the FeliCa communication scheme. The receiver part provides a robust and efficient implementation of the demodulation and decoding circuitry for FeliCa coded signals. The digital part handles the FeliCa framing and error detection like CRC. The CLRC663 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions. The CLRC663 supports vicinity protocoll according ISO/IEC15693, EPC UID and ISO/IEC 18000-3 mode 3. The complete vicinity product family of NXP is supported and enable a readability for mid-ranger reader applications.
The following host interfaces are provided:
The LPC1227 are ARM Cortex-M0 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M0 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. In addition to the ARM Cortex-M0, the LPC1X features an event handler API to limit the interrupt load of the ARM Cortex-M0 CPU and to allow for additional power-savings by off-loading event handling from the main CPU.
The LPC1227 operates at CPU frequencies of up to 33 MHz and include up to 128 kB of flash memory and 8 kB of data memory.
Not all connnections of the LPC1227 product are implemented by the PRH600.