Audio and Video (A/V) Receiver

Block Diagram

AV Receiver

AV Receiver BD

Supported Devices

Interfaces

USB PD-PHY and CC-Logic

Automotive Ethernet PHYs

Analog and Mixed Signal

Analog Switches

Processors and Microcontrollers

LPC800 Arm Cortex-M0+

i.MX 8 Applications Processors

Wireless Connectivity

Wi-Fi® + Bluetooth® + 802.15.4

RFID

Connected NFC Tags

Power Management

PMICs

Battery Chargers

Load Switches

Sensors

I3C/I²C Digital Temp. Sensors

Features

Multicore Processing

  • Voltage range: 2.7 to 5.5 V
  • 4x Cortex-A53 core platforms up to 1.8GHz per core
  • 32KB L1-I Cache/ 32 kB L1-D Cache
  • 512 kB L2 Cache
  • 1x Cortex-M4 core up to 400MHz
  • 16 kB L1-I Cache/ 16 kB L2-D Cache

Key Features

  • 3D GPU (1x shader, OpenGL® ES 2.0)
  • Display Interface 1x MIPI DSI (4-lane) with PHY
  • 1080p60 VP9 Profile 0, 2 (10-bit) decoder, HEVC/H.265 decoder, AVC/H.264 Baseline, Main, High decoder, VP8 decoder
  • 1080p60 AVC/H.264 encoder, VP8 encoder
  • Audio 5x SAI (12Tx + 16Rx external I2S lanes), 8ch PDM input

Documentation

Quick reference to our documentation types.

15 documents

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Support

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