Transformer Terminal Unit (TTU)

Block Diagram

Transformer Terminal Unit (TTU)

Transformer Terminal Unit BD

Supported Devices

Analog and Mixed Signal

Voltage Level Translators

Real-Time Clocks

Wireless Connectivity

Bluetooth Low Energy

Power Management

PMICs

Sensors

I3C/I²C Digital Temp. Sensors

Processors and Microcontrollers

Layerscape Processors

Features

Core Complex and Networking Elements

  • Quad (LS1043A) or Dual (LS1023A) Arm® Cortex®-A53 64-bit cores
  • 1 GHz to 1.6 GHz
  • 32/32 I/D Cache KB L1 and 1 MB L2 cache
  • Up to seven 1x GbE or 1x 10GbE and five x GbE
  • Four-lane SerDes up to 10 GHz multiplexed across controllers supporting: Three PCI Express® Gen 2 interfaces, SATA 3.0 Interface and uQUICC Engine

Accelerators, Basic Peripherals and Memory Control

  • DPAA Parse, Classify and Distribution Engines
  • Integrated security engine
  • DDR 3L/4
  • Three USB 3.0 interfaces with PHY
  • QuadSPI
  • IFC Flash

Additional Features

  • QorIQ Platform's Trust Architecture
  • Arm SMMU for hardware-enhanced virtualization
  • 0.9V options for lowest power designs
  • 23x23 package options for pin compatible performance scaling

Documentation

Quick reference to our documentation types.

8 documents

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Support

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