Terrestrial Digital Radio Processor

Product Details

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Features

DAB, DAB+ and T-DMB Radio Technology

  • DAB, DAB+ and T-DMB baseband signal decoding and processing
  • Data services and background scanning DAB, DAB+ and T-DMB support for second ensemble
  • Front end to baseband interface support through both serial BB_I2S interface and/or parallel baseband bus type interface
  • Secondary baseband interface for dual tuner applications either with serial BB_I2S interface or parallel baseband bus type interface
  • Contact NXP Semiconductors for details on supported DAB, DAB+, T-DMB capabilities of SAF3561:
    • Metadata support for digital radio
    • Data services support for digital radio
    • Program services support for digital radio
    • Seamless blending with an FM or second DAB audio service
    • Advanced audio error concealment features
    • Impulse noise and spur cancelation
  • Support for multiple RF tuner frontends (Contact NXP Semiconductors for a list of supported RF tuner frontends)

Digital Audio

  • Up to 6 channel (5.1) audio support through I2S-bus serial audio interface
  • Optional SRC (8 kHz to 48 kHz) for up to 6 channels of I2S-bus audio output
  • I2S-bus serial audio input for auxiliary processing
  • Optional SRC (8 kHz to 48 kHz) for I2S-bus input
  • Optional restricted support for 96 kHz input and output sample-rate conversion
  • Optional digital audio output through S/PDIF (without SRC)
  • Basic audio processing for external digital audio sources
  • Advanced audio processing (Contact NXP Semiconductors for a list of supported audio processing features)

Memory

  • Supports SDR-SDRAM controller (up to 512 Mbit in 16-bit configuration)
  • Supports serial NOR-Flash memory with various sizes depending on the actual application

Other Peripheral Interfaces

  • Two I2C-bus interfaces
  • Three Serial Peripheral Interfaces (SPI)
  • One UART interface with flow control or two UART interfaces w/o flow control
  • Five individual GPIO pins for applications and diagnostics
  • One JTAG interface for diagnostics

Miscellaneous

  • One internal clock oscillator and two internal Phase-Locked Loops (PLL)
  • Can run on external crystal or reference clock from external IC
  • Powerful signal and audio processing core architecture
  • Qualified in accordance with AEC-Q100

Design Resources

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Documentation

Quick reference to our documentation types.

2 documents

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