Parallel Bus to 1 Channel Fm+ I2C-Bus Controller

PCA9661B
  • Not Recommended for New Designs
  • This page contains information on a product that is not recommended for new designs.

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Product Details

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Block Diagram

PCA9661 BLOCK DIAGRAM

PCA9661 BLOCK DIAGRAM

Features

Key Features

  • Parallel-bus to I2C-bus protocol converter and interface
  • 1 Mbit/s and up to 30 mA SCL/SDA IOL Fast-mode Plus (Fm+) capability
  • Internal oscillator trimmed to 1 % accuracy reduces external components
  • 4352-byte buffer for the Fm+ channel
  • Communicates with up to 64 followers in one serial sequence
  • Sequence looping with interval timer
  • Supports SCL clock stretching
  • JTAG port available for boundary scan testing during board manufacturing process
  • Trigger input synchronizes serial communication exactly with external events
  • Maskable interrupts
  • Fast-mode Plus I2C-bus capable and compatible with SMBus

3 Reset Levels

  • Individual software channel reset
  • Global software reset
  • Global hardware RESET pin

Operating Supply Voltage

  • 3.0 V to 3.6 V (device and host interface)

I2C-Bus I/O Supply Voltage

  • 3.0 V to 5.5 V

Latch-Up Testing

  • Done to JEDEC Standard JESD78, which exceeds 100 mA

ESD Protection

  • Exceeds 8000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101

Packages

  • LQFP48

Design Resources

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Documentation

Quick reference to our documentation types.

5 documents

Hardware

1 hardware offering

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