Design Files
1 design file
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Symbols and Footprints
PCA9663B-LQFP48-CAD Symbol and PCB Footprint – BXL File
Parallel Bus to Three-Channel Fm+ I²C-Bus Controller
PCA9663B Receive alerts
The PCA9663 is an advanced single leader mode I²C-bus controller. It is a fourth generation bus controller designed for data intensive I²C-bus data transfers. It has three independent I²C-bus channels with data rates up to 1 Mbits/s using the Fast-mode Plus (Fm+) open-drain topology. Each channel has a generous 4352 byte data buffer which makes the PCA9663 the ideal companion to any CPU that needs to transmit and receive large amounts of serial data.
The PCA9663 is a 8-bit parallel-bus to I²C-bus protocol converter. Each channel can be configured to communicate with up to 64 followers in one serial sequence with no intervention from the CPU. The controller also has a sequence loop control feature that allows it to automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I²C-bus and for the interval timer used in sequence looping. This feature greatly reduces CPU overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external everts. The trigger signal controls the rate at which a stored sequence is re-transmitted over the I²C-bus.
Error reporting is handled at the transaction level, channel level and controller level with a simple interrupt tree and interrupt masks allow further customization of interrupt management.
The controller and parallel bus interfaces run at 3.3 V and the I²C-bus I/Os are 5 V tolerant with logic levels referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.
Outline 3d SOT313-2
Product Details
Features
System Features
- Parallel-bus to I²C-bus protocol converter and interface
- 1 Mbit/s and up to 30 mA SCL/SDA IOL Fast-mode Plus (Fm+) capability
- Internal oscillator trimmed to 1 % accuracy reduces external components
- Individual 4352-byte buffers for the Fm+ channels for a total of 13056 bytes of buffer space
- Three levels of reset: individual software reset, global software reset, global hardware RESET pin
- Communicates with up to 64 followers on each channel in one serial sequence
- Sequence looping with interval timer
- Supports SCL clock stretching
- JTAG port available for boundary scan testing during board manufacturing process
- Trigger input synchronizes serial communication exactly with external events
- Maskable interrupts
- Fast-mode Plus I²C-bus capable and compatible with SMBus
- Operating supply voltage: 3.0 V to 3.6 V (device and host interface)
- I²C-bus I/O supply voltage: 3.0 V to 5.5 V
- Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
- ESD protection exceeds 8000 V HBM per JESD22-A114, and 1000 V CDM per JESD22-C101
- Packages offered: LQFP48
- Add I²C-bus port to controllers/processors that do not have one
- Add additional I²C-bus ports to controllers/processors that need multiple I²C-bus ports
- Converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire printed-circuit board
- Entertainment systems
- LED matrix control
- Data intensive I²C-bus transfers
Documentation
Quick reference to our documentation types.
5 documents
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User Guide
I2C-bus specification and user manual
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Package Information
plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
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Supporting Information
Footprint for wave soldering
Design Resources
Hardware
Engineering Services
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2 engineering services
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Independent Design House (IDH)
Embedded Software Design
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Independent Design House (IDH)
Hardware Design Services
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