Parallel Bus to Three-Channel Fm+ I²C-Bus Controller

PCA9663B

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Block Diagram

PCA9663 BLOCK DIAGRAM

PCA9663 BLOCK DIAGRAM

Features

System Features

  • Parallel-bus to I²C-bus protocol converter and interface
  • 1 Mbit/s and up to 30 mA SCL/SDA IOL Fast-mode Plus (Fm+) capability
  • Internal oscillator trimmed to 1 % accuracy reduces external components
  • Individual 4352-byte buffers for the Fm+ channels for a total of 13056 bytes of buffer space
  • Three levels of reset: individual software reset, global software reset, global hardware RESET pin
  • Communicates with up to 64 followers on each channel in one serial sequence
  • Sequence looping with interval timer
  • Supports SCL clock stretching
  • JTAG port available for boundary scan testing during board manufacturing process
  • Trigger input synchronizes serial communication exactly with external events
  • Maskable interrupts
  • Fast-mode Plus I²C-bus capable and compatible with SMBus
  • Operating supply voltage: 3.0 V to 3.6 V (device and host interface)
  • I²C-bus I/O supply voltage: 3.0 V to 5.5 V
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • ESD protection exceeds 8000 V HBM per JESD22-A114, and 1000 V CDM per JESD22-C101
  • Packages offered: LQFP48
  • Add I²C-bus port to controllers/processors that do not have one
  • Add additional I²C-bus ports to controllers/processors that need multiple I²C-bus ports
  • Converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire printed-circuit board
  • Entertainment systems
  • LED matrix control
  • Data intensive I²C-bus transfers

Documentation

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5 documents

Design Resources

Design Files

1 design file

Hardware

1 hardware offering

Engineering Services

2 engineering services

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