I²C-Bus Extender

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Block Diagram

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P82B715 Block Diagram

P82B715 Block Diagram

Block diagram: P82B715PN, P82B715TD

Features

General Features

  • Dual, bidirectional, unity voltage gain buffer with no external directional control required
  • Compatible with I2C-bus and its derivatives SMBus, PMBus, DDC, etc.
  • Logic signal levels may include (but not exceed) both supply and ground
  • Logic signal input voltage levels are output without change and are independent of VCC
  • x10 impedance transformation, but does not change logic voltage levels
  • Supply voltage range 3 V to 12 V
  • Clock speeds to at least 100 kHz and 400 kHz when other system delays permit
  • ESD protection exceeds 2500 V HBM per Mil. Std 883C-3015.7 and 400 V MM per JESD22-A115 (I/Os have diodes to VCC and GND)
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Increase the total connected capacitance of an I2C-bus system to around 3000 pF
  • Drive IC-bus signals over long cables to approximately 50 meters or 3000 pF
  • Drives x10 lower impedance bus wiring for improved noise immunity
  • Multi-drop distribution of IC-bus signals using low cost twisted-pair cables
  • AdvancedTCA radial IPMB architecture
  • Driving 30 mA Fm+ devices from standard 3 mA parts

Design Resources

Documentation

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Design Files

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Hardware

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Engineering Services

2 engineering services

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