The PCA9605 is a monolithic CMOS integrated circuit for bus buffering in applications including I²C-bus, SMBus, DDC, PMBus, and other systems based on similar principles.
The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing the maximum permissible bus capacitance on both sides of the buffer.
The PCA9605 includes a unidirectional buffer for the clock signal, and a bidirectional buffer for the data signal. Follower devices which employ clock stretching are therefore not supported.
In its most basic implementation, the buffer will allow an extended number of follower devices to be attached to one (or more) leader devices. In this case, all leader devices would be positioned on the Sxx_IN side of the PCA9605.
The direction pin (DIR) further enhances this function by allowing the unidirectional clock signal to be reversed, thus allowing leader devices on both sides of the buffer.
The enable (EN) function allows sections of the bus to be isolated. Individual parts of the system can be brought on-line successively. This means a controlled start-up using a diverse range of components, operating speeds and loads is easily achieved.
To get further assistance directly from NXP, please see our Engineering Services.
2 engineering services
To find a complete list of our partners that support this product, please see our Partner Marketplace.