Enhanced Octal Universal Asynchronous Receiver/Transmitter (Octal UART)


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Block Diagram

SCC2698BC1A84, SCC2698BE1A84 Block Diagram

SCC2698BC1A84, SCC2698BE1A84 Block Diagram


  • Eight full-duplex independent asynchronous receiver/transmitters
  • Quadruple buffered receiver data register
  • Programmable data format:
    • 5 to 8 data bits plus parity
    • Odd, even, no parity or force parity
    • 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
  • Baud rate for the receiver and transmitter selectable from:
    • 26 fixed rates: 50 to 38.4K baud

      Non-standard rates to 115.2K baud

    • User-defined rates from the programmable counter/timer

      associated with each of four blocks

    • External 1x or 16x clock
  • Parity, framing, and overrun error detection
  • False start bit detection
  • Line break detection and generation
  • Programmable channel mode
    • Normal (full-duplex), automatic echo, local loop back, remote loopback
  • Four multi-function programmable 16-bit counter/timers
  • Four interrupt outputs with eight maskable interrupting conditions for each output
  • Receiver ready/FIFO full and transmitter ready status available on 16 multi-function pins in PLCC package
  • On-chip crystal oscillator
  • TTL compatible
  • Single +5V power supply with low power mode
  • Eight multi-purpose output pins
  • Sixteen multi-purpose I/O pins
  • Sixteen multi-purpose Input pins with pull-up resistors


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