PCK2002DL: 0-300 MHz I2C 1:18 clock buffer ARCHIVED

Overview

Archived content is no longer updated and is made available for historical reference only.

The PCK2002 is a 1-18 fanout buffer used for 133/100 MHz CPU, 66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock distribution. 18 outputs are typically used to support up to 4 SDRAM DIMMS commonly found in desktop, workstation or server applications.

All clock outputs meet Intel?s drive, rise/fall time, accuracy, and skew requirements. An I²C interface is included to allow each output to be enabled/disabled individually. An output disabled via the I²C interface will be held in the LOW state. In addition, there is an OE input which 3-States all outputs.

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Features

HIGH speed, LOW noise non-inverting 1-18 buffer
Typically used to support four SDRAM DIMMs
Multiple V_DD, V_SS pins for noise reduction
3.3 V operation
Separate 3-State pin for testing
ESD protection exceeds 2000 V per Standard 801.2
Optimized for 66 MHz, 100 MHz and 133 MHz operation
Typical 175 ps skew outputs
Available in 48-pin SSOP and TSSOP packages
See PCK2002M for mobile (reduced pincount) 28-pin 1-10 buffer version
Spread spectrum compliant
Individual clock output enable/disable via I²C

MoreLess

Features

HIGH speed, LOW noise non-inverting 1-18 buffer
Typically used to support four SDRAM DIMMs
Multiple V_DD, V_SS pins for noise reduction
3.3 V operation
Separate 3-State pin for testing
ESD protection exceeds 2000 V per Standard 801.2
Optimized for 66 MHz, 100 MHz and 133 MHz operation
Typical 175 ps skew outputs
Available in 48-pin SSOP and TSSOP packages
See PCK2002M for mobile (reduced pincount) 28-pin 1-10 buffer version
Spread spectrum compliant
Individual clock output enable/disable via I²C

Data Sheets

Outline 3d SOT370-1

Outline 3d SOT370-1

Outline 3d SOT370-1

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