8-Bit Microcontroller with Accelerated Two Clock 80C51 Core 8 KB/16 KB 3 V Byte-Erasable Flash with 10-Bit ADC

P89LPC954FA

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Features

Principal features
  • 8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
  • 256-byte RAM data memory and a 256-byte auxiliary on-chip RAM.
  • 8-input multiplexed 10-bit ADC with window comparator that can generate an interrupt for in or out of range results. Two analog comparators with selectable inputs and reference source.
  • Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output) and a 23-bit system timer that can also be used as a RTC.
  • Two enhanced UARTs with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I²C-bus communication port and SPI communication port.
  • High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. Fast switching between the internal RC oscillator and any oscillator source provides optimal support of minimal power active mode with fast switching to maximum performance.
  • 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).
  • 44-pin and 48-pin packages with 40 and 42 I/O pins minimum while using on-chip oscillator and reset options.
  • Port 5 has high current sourcing/sinking (20 mA) for all Port 5 pins. All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip.
  • Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values.

Additional features

  • A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.
  • Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.
  • Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application.
  • In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application.
  • Low voltage (brownout) detect allows a graceful system shutdown when power fails. May optionally be configured as an interrupt.
  • Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 uA (total power-down with voltage comparators disabled).
  • On-chip power-on reset allows operation without external reset components. A software reset function is also available.
  • Programmable external reset pin (P1.5) configuration options: open drain bidirectional reset input/output, reset input with pull-up, push-pull reset output, input-only port. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets.
  • Only power and ground connections are required to operate the P89LPC952/954 when internal reset option is selected.
  • Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz.
  • Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.
  • Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only.
  • Port 'input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.
  • Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.
  • Four interrupt priority levels.
  • Eight keypad interrupt inputs, plus two additional external interrupt inputs.
  • Schmitt trigger port inputs.
  • Second data pointer.
  • Extended temperature range.
  • Emulation support.

Documentation

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Design Files

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  • Models

    IBIS models for LPC9xx

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