DSP56004: Audio DSP ARCHIVED

Overview

This product has been designated as an "End Of Life Buy" and is not recommended for NEW designs.

The DSP56004 is a high-performance, programmable Digital Signal Processor (DSP) suitable for a variety of cost-sensitive audio functions, such as Dolby Pro Logic decoding and Lucasfilm Home THX; enhancements.

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Features

Digital Signal Processing Core

Efficient, object code compatible, 24-bit 56000 family DSP engine

Up to 33 Million Instructions Per Second (MIPS) - 30.3 ns instruction cycle at 66 MHz
Up to 180 Million Operations Per Second (MOPS) at 66 MHz
Highly parallel instruction set with DSP addressing modes
Two 56-bit accumulators including extension byte
Parallel 24 x 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
Double precision 48 x 48-bit multiply with 96-bit result in 6 instruction cycles
56-bit addition/subtraction in 1 instruction cycle
Fractional and integer arithmetic with support for multiprecision arithmetic
Hardware support for block-floating point Fast Fourier Transforms (FFT)
Hardware nested DO loops
Zero-overhead fast interrupts (2 instruction cycles)
Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories

Memory

Table 1 lists the memory configurations of the DSP56004.

On-chip Harvard architecture permitting simultaneous accesses to program and two data memories
512 x 24-bit on-chip Program RAM and 64 x 24-bit bootstrap ROM
- On the DSP56004ROM this program memory is replaced with 2560 x 24-bit on-chip Program ROM*, 256 x 24-bit on-chip Program RAM, and the 64 x 24-bit bootstrap ROM
Two 256 x 24-bit on-chip data RAMs
Two 256 x 24-bit on-chip data ROMs containing sine and logarithm tables
- On the DSP56004ROM these data ROMs contain developer-provided data
Bootstrap loading from Serial Host Interface or External Memory Interface

Proprietary bootstrap for securing Program ROM contents

DSP56004 Memory Configurations
Part Type	Program		X Data		Y Data
Part Type	ROM	RAM	ROM	RAM	ROM	RAM
DSP56004	none	512	256 log2X	256	256 sine	256
DSP56004ROM	2560*	256	256*	256	256*	256

Word width is 24-bits.

Peripheral and Support Circuits

Serial Audio Interface (SAI) includes two receivers and three transmitters, leader or follower capability, and implementation of I2S, Sony, and Matshushita audio protocols; two sets of SAI interrupt vectors
Serial Host Interface (SHI) features single leader capability, 10-word receive FIFO, and support for 8-, 16- and 24-bit words
External Memory Interface (EMI), implemented as a peripheral supporting:
Page-mode DRAMs (one or two chips): 64 k x 4, 256 k x 4, and 4 M x 4 bits
SRAMs (one to four): 256 k x 8 bits
Data bus may be 4 or 8 bits wide
Data words may be 8, 12, 16, 20, or 24-bits wide
Four dedicated, independent, programmable General Purpose I/O (GPIO) lines
On-chip peripheral registers memory mapped in data memory space
Three external interrupt request pins
On-Chip Emulation (OnCE^TM) port for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer for the core clock
Power-saving Wait and Stop modes
Fully static, HCMOS design for operating frequencies from 40, 50, and 66 MHz down to DC
80-pin plastic Quad Flat Pack surface-mount package; 14 x 14 x 2.45 mm; 0.65 mm lead pitch
Completely pin-compatible with the DSP56007 for easy upgrades
5 V power supply

The DSP56004ROM is a ROM-based version of the RAM-based DSP56004. The DSP56007 is a pin-compatible version of the DSP56004 with a different memory configuration.