MFR4200: FlexRay Communication Controller ARCHIVED

Overview

The NXP^® MFR4200 is the world's first FlexRay communication controller to enter production. The MFR4200 provides system designers with the advanced networking features defined by the flexray consortium. This device is designed for easy integration with a wide range of MCUs such as Our successful lines of S12X, Power Architecture MPC5xx and MPC55xx, and Digital Signal Controllers. The MFR4200 includes a rich set of features that enables robust networking solutions which are high bandwidth, deterministic, highly reliable, and share a global timebase.

Archived content is no longer updated and is made available for historical reference only.

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Features

Bit rate up to a maximum of 10 Mbit/sec on each of two channels.
59 message buffers, each with a payload of up to 32 bytes of data.
FlexRay frames with up to 254 payload data bytes. Padding is used for FlexRay payload data which exceeds 32 byte data size boundary.
One configurable Receive FIFO.
Each message buffer configurable as Receive buffer, Transmit buffer (single or double) or as part of the Receive FIFO.
Two Receive receive shadow buffers available for each channel.
Message buffer configurable with state or event semantics.
Flexible Error Signaling mechanism which provides 8 configurable counters, slot status indicators and interrupts.
Internal measured time difference values used for the Clock Synchronization are read accessible through the CHI.
The status of up to four slots can be observed independently of the communication controller receive buffers.
The host accesses all message buffers by means of three Active Message buffers (Active Transmit buffer, Active Receive buffer and Active Receive FIFO buffer) in the CHI.
Configurable message filtering based on frame ID, cycle counter and channel for Transmit and Receive buffers.
Configurable message filtering based on frame ID, channel and message ID for Receive FIFO.
Duration of the communication cycle configurable in microticks.

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Features

Bit rate up to a maximum of 10 Mbit/sec on each of two channels.
59 message buffers, each with a payload of up to 32 bytes of data.
FlexRay frames with up to 254 payload data bytes. Padding is used for FlexRay payload data which exceeds 32 byte data size boundary.
One configurable Receive FIFO.
Each message buffer configurable as Receive buffer, Transmit buffer (single or double) or as part of the Receive FIFO.
Two Receive receive shadow buffers available for each channel.
Message buffer configurable with state or event semantics.
Flexible Error Signaling mechanism which provides 8 configurable counters, slot status indicators and interrupts.
Internal measured time difference values used for the Clock Synchronization are read accessible through the CHI.
The status of up to four slots can be observed independently of the communication controller receive buffers.
The host accesses all message buffers by means of three Active Message buffers (Active Transmit buffer, Active Receive buffer and Active Receive FIFO buffer) in the CHI.
Configurable message filtering based on frame ID, cycle counter and channel for Transmit and Receive buffers.
Configurable message filtering based on frame ID, channel and message ID for Receive FIFO.
Duration of the communication cycle configurable in microticks.

Data Sheets

Application Notes

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