PXN20: Power Architecture MCU, 116 MHz, Dual-Core, Networking ARCHIVED

Overview

The 32-bit dual core PXN20 Power Architecture^® microcontrollers support a variety of communication protocols allowing the designer to put together a cost-effective, reliable industrial gateway with cutting-edge performance. A large amount of on-chip flash, on-chip SRAM with error correction code capability, 36-channel ADC, dual cores and a host of serial I/Os make the PXN20 a compelling solution for your next design cycle.

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Features

Dual processors: e200z6 and e200z0 CPU architecture
Up to 592 KB on-chip SRAM with 2 MB on-chip flash
32-channel DMA and 36-channel ADC, 10-bit
EEPROM emulated in program flash (16 KB sectors)
UART: up to 12x, SPI: 3x, CAN: 6x, and I²C: 4x
Ethernet support fast Ethernet controller (FEC)
Debug support JTAG interface, Nexus 3
Timed I/Os: eMIOS 24-channel, 16-bit
Internal timers: programmable interrupt timers (PIT) 8-channel, 32-bit
Max core speed 116 MHz with Low-power modes

MoreLess

Features

Dual processors: e200z6 and e200z0 CPU architecture
Up to 592 KB on-chip SRAM with 2 MB on-chip flash
32-channel DMA and 36-channel ADC, 10-bit
EEPROM emulated in program flash (16 KB sectors)
UART: up to 12x, SPI: 3x, CAN: 6x, and I²C: 4x
Ethernet support fast Ethernet controller (FEC)
Debug support JTAG interface, Nexus 3
Timed I/Os: eMIOS 24-channel, 16-bit
Internal timers: programmable interrupt timers (PIT) 8-channel, 32-bit
Max core speed 116 MHz with Low-power modes

Data Sheets

PXN20 Microcontroller Block Diagram

PXN20 Microcontroller Block Diagram

PXN20 Microcontroller Block Diagram

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