MC92603: Quad - Gigabit Ethernet SerDes Transceiver ARCHIVED

Product Highlights

Common Features

• Four independent SerDes channels with full-duplex differential data links
• Configurable as a dual to provide redundant transmit and receive serial links
• Selectable speed range: 1.25 Gbaud or 0.625 Gbaud
• Internal 8B/10B encoder/decoders
• Source synchronous parallel data interfaces
• Selectable source-aligned or source-centerd timing on receiver output interfaces
• Double Data Rate (RGMII/RTBI), source synchronous 4-/5-bit optional interfaces
• Links drive 50 Ohm or 75 Ohm media (100 or 150 Ohm differential), backplane or cable
• Link inputs have on-chip receiver link termination and are "hot-swap" compatible
• Low power: <1 W, under typical conditions, while operating in backplane mode with all transceivers at full speed</LI />
• Unused transceiver channels may be individually disabled to reduce power consumption
• IEEE Std. 1149.1 JTAG support and full-speed built=in self test functions

Backplane Application Features

• Link-to-link synchronization supports aligned, multi-channel, word transfers. Synchronization mechanism tolerates up to 40 bit-times of link-to-link media delay skew
• Supports Disparity Based Word Sync Events for compatibility with legacy transceivers
• Selectable COMMA code group alignment mode enables aligned or unaligned transfers

Ethernet Friendly Features

• GMII, TBI, RGMII or RTBI data interface options
• COMMA code group alignment in receivers
• Provides the PCS and PMA layers for Ethernet PHYs as specified in IEEE Std. 802.3-2002
• MDIO slave interface and registers as defined in IEEE Std. 802.3-2002 are fully supported
• Supports rate adaption within IPG for jumbo frames up to 14 Kbytes

Typical Applications

• High-density board applications for communications designs utilizing IEEE Std. 802.3 protocol
• High-speed data transfer applications in high-bandwidth backplane and chassis-to-chassis networking
• PHY interface to NXP^® C-Port (C-3e or C-5^®e) network processors and Power QUICC III (MPC8540 or MPC8560 )communications processors

Technical Specifications

• All channels have:
  • 8B/10B encoder/decoder that can be enabled or bypassed in Ten-Bit mode
  • Clock generation/recovery
  • Independent 8-bit (GMII) or 10-bit (TBI) system I/F with parallel-to-serial, serial-to-parallel conversion
• Transmit data clock is selectable between per-channel transmit clock or channel "A" transmit clock
• Received data may be clocked at the recovered clock or the reference clock frequencies
• Half frequency, split-phase recovered clock in TBI (10-bit) mode
• Transceiver Links operate over 50-Ohm or 75-Ohm media (100 or 150 Ohm differential) for lengths of up to 1.5 meters of FR-4 board/back-plane, or ten meters of coax
• No external loop filter components required
• System BIST test modes with error counter
• Loopback BIST isolated from link inputs and outputs
• IEEE Std. 1149.1 JTAG boundary scan support
• LVPECL differential reference clock input with single-ended LVTTL reference clock input option (125 MHz max)
• Two single ended buffered Ref Clock outputs provided for associated logic interfaces
• Frequency offset tolerance between tansmitter and receiver in excess of >250ppm
• Package: 256pin MAPBGA (17x17mm body size, 1.0 mm ball pitch)