DSP56011: Symphony^® Digital Audio DSP ARCHIVED

• Efficient, object-code compatible, 24-bit DSP56000 family DSP engine
  • 40.5 Million Instructions Per Second (MIPS); 24.69 ns instruction cycle at 81 MHz
  • Highly parallel instruction set with unique DSP addressing modes
  • Two 56-bit accumulators, including extension byte
  • Parallel 24 x 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
  • Double precision 48 x 48-bit multiply with 96-bit result in 6 instruction cycles
  • 56-bit addition/subtraction in 1 instruction cycle
  • Fractional and integer arithmetic with support for multi-precision arithmetic
  • Hardware support for block-floating point Fast Fourier Transforms (FFT)
  • Hardware nested DO loops
  • Zero-overhead fast interrupts (2 instruction cycles)
  • PLL-based clocking with a wide range of frequency multiplications (1 to 4096) and power saving clock divider (2i : i = 0 to 15), which reduces clock noise
  • Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories

• Modified Harvard architecture allows simultaneous access to program and data memories
• 12800 x 24-bit on-chip Program ROM*
• 4096 x 24-bit on-chip X-data RAM and 3584 x 24-bit on-chip X-data ROM*
• 4352 x 24-bit on-chip Y-data RAM and 2048 x 24-bit on-chip Y-data ROM*
• 512 x 24-bit on-chip Program RAM and 64 x 24-bit bootstrap ROM
• As much as 2304 x 24-bits of X- and Y-data RAM can be switched to Program RAM, giving a total of 2816 x 24-bits of Program RAM

Table 1 lists the memory configurations of the DSP56011.

* These ROMs may be factory programmed with data/program provided by the application developer.

• Serial Audio Interface (SAI) includes two receivers and three transmitters, master or slave capability, and implementation of I2S, Sony, and Matshushita audio protocols; two sets of SAI interrupt vectors
• Serial Host Interface (SHI) features single master capability, SPI and I2C protocols, 10-word receive FIFO, and support for 8-, 16- and 24-bit words
• Byte-wide Parallel Host Interface with DMA support capable of reconfiguration as fifteen General Purpose Input/Output (GPIO) lines
• Digital Audio Transmitter (DAX) features one serial transmitter capable of supporting SPDIF, IEC958, CP-340, and AES/EBU formats
• Eight dedicated, independent, programmable GPIO lines
• On-chip peripheral registers memory mapped in data memory space
• OnCE port for unobtrusive, processor speed-independent debugging
• Software programmable PLL-based frequency synthesizer for the core clock
• Power saving Wait and Stop modes
• Fully static, HCMOS design for operating frequencies from 81 MHz down to DC
• 100-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package
• 5 V power supply