Enhanced Performance HDMI/DVI Level Shifter with Inverting HPD


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High-speed TMDS level shifting
  • Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals
  • TMDS level shifting operation up to 2.5 Gbit/s per lane (250 MHz character clock)
  • Integrated 50 Ω termination resistors for self-biasing differential inputs
  • Back-current safe outputs to disallow current when device power is off and monitor is on
  • Disable feature to turn off TMDS inputs and outputs and to enter low-power state

DDC level shifting

  • Integrated DDC level shifting (3.3 V source to 5 V sink side)
  • 0 Hz to 400 kHz I²C-bus clock frequency
  • Back-power safe sink-side terminals to disallow backdrive current when power is off or when DDC is not enabled

HPD level shifting

  • HPD inverting level shift from 0 V on the sink side to 1.1 V on the source side, or from 5 V on the sink side to 0 V on the source side
  • Integrated 200 kΩ pull-down resistor on HPD sink input guarantees 'input LOW' when no display is plugged in
  • Back-power safe design on HPD_SINK to disallow backdrive current when power is off


  • Power supply 3.3 V +- 10 pct
  • ESD resilience to 8 kV HBM, 500 V CDM
  • Power-saving modes (using output enable)
  • Back-current-safe design on all sink-side main link, DDC and HPD terminals
  • Transparent operation: no re-timing or software configuration required


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