5G

5G-BLOCK-DIAGRAM

Block Diagram

Choose a diagram:

Customer Premises Equipment

5G Customer Premises Equipment BD

Central Unit

5G Central Unit BD

Distributed Unit

5G Distributed Unit BD

Radio Unit

5G Radio Unit BD

Supported Devices

Interfaces

High-Speed Multiplexer

USB Redrivers

I2C Multiplexers/Switches

General Purpose I/O (GPIO)

Analog and Mixed Signal

Real-Time Clocks

Analog Switches

Voltage Level Translators

Wireless Connectivity

Bluetooth Low Energy

RF

Legacy 5G mmWave

Sensors

I3C/I²C Digital Temp. Sensors

Power Management

PMICs

Processors and Microcontrollers

Layerscape Processors

LX2160A Features

  • 16 Cortex®-A72 CPU cores, running up to 2.2 GHz
  • 18 MB cache/on-chip memory
  • 24 SerDes lanes, operating up to 25 GHz
  • Up to 16 Ethernet ports
  • Supported Ethernet speeds include 1, 2.5, 10, 25, 40, 50, and 100 gigabits per second
  • 114 Gbps Layer 2 Ethernet switch

LS1046A Features

  • Four Cortex-A72 cores
  • 2 MB L2 cache
  • 2x 10 GbE, 1x 2.5 GbE, and 5x GbE
  • Eight-lane SerDes up to 10 GHz multiplexed across controllers supporting:
  • DPAA Parse, Classify, and Distribution Engines
  • Integrated security engine
  • 3x PCIe 3.0 Controllers, x4, x2, x1

LA12xx Features

  • > 1 TFLOPs VSPA Vector Engine performance
  • Integrated High Speed and Low Speed ADC/DACs for mmWave and sub-6 GHz applications
  • High performance Polar and LDCP Forward Error Correction / HARQ engine
  • 50 Gbit/s of PCIe I/O
  • 4-8x VSPA3-16@ < 640 MHz (=1.3 TFLOP)
  • Floating point SIMD compute, 32 CMAC HP /clock
  • 2 MB on-chip SRAM

Documentation

Quick reference to our documentation types.

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