Transport Barrier System


Block Diagram

Transport Barrier System

Transport Barrier System BD

Supported Devices

Security and Authentication

Contact Readers


I3C/I²C Digital Temp. Sensors

Processors and Microcontrollers

K8x Secure

i.MX 6 Processors


NFC Readers

Power Management


Analog and Mixed Signal

Real-Time Clocks


K81 Memory and Scalability

  • 256 KB of Flash
  • 256 KB of SRAM
  • CPU cache consisting of separate 8 KB I/D and 8 KB system cache
  • QSPI controller optimized for XIP from external serial NOR flash memories with support for quad and octal data interfaces
  • SDRAM and external memory bus interfaces
  • eMMC/SDIO interface through eSDHC peripheral

i.MX 6ULL CPU Complex and Display

  • Cortex-A7 core up to 900 MHz, 128 KB L2 cache
  • Parallel LCD Display up to WXGA (1366x768)
  • 8/10/16/24-bit Parallel Camera Sensor Interface
  • Electrophoretic display controller support direct-driver for E-Ink EPD panel, with up to 2048x1536 resolution at 106 Hz


  • 16-bit LP-DDR2, DDR3/DDR3L
  • 8/16-bit Parallel NOR FLASH / PSRAM
  • Dual-channel Quad-SPI NOR FLASH
  • 8-bit Raw NAND FLASH with 40-bit ECC


  • 2x MMC 4.5/SD 3.0/SDIO Port
  • 2x USB 2.0 OTG, HS/FS, Device or Host with PHY
  • Audio Interfaces include 3x I2S/SAI, S/PDIF Tx/Rx
  • 2x 10/100 Ethernet with IEEE 1588
  • 2x 12-bit ADC, up to 10 input channel total, with resistive touch controller (4-wire/5-wire)


Quick reference to our documentation types.

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