NFC Frontend supporting challenging RF environment for payment, physical access control

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Product Details

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Block Diagram

PN5190 Block Diagram

PN5190 System Block Diagram


  • High power (2W), feature-filled transmitter: DPC 2.0 (dynamic power control without processing load on host MCU)
  • Single 3.3 V supply with max TX transmitter power possible
  • Connection of 1 differential or 2 single-ended antennas
  • Robust receiver: Automatic configuration, advanced insensitivity against TFT display noise for higher RF performance
  • Full NFC Frontend with active load modulation in Card Mode for large operating distance
  • All relevant RF protocols implemented
  • NXP proprietary high datarates up to 212 Kbit for NTAG5 communication
  • Ultra-low-power card detect for low average current consumption
  • Flexible configuration of EMD handling (EMVCo 3.1, ISO, FeliCa) for future-proof system integration
  • Automatic antenna tuning (AAT) with variable capacitors
  • RF Debugging without external probing of test signals possible but not required – ideal debugging solution for PCI compliant POS terminals
  • Advanced RF debugging with AUX0, AUX1, AUX2 outputs
  • Certifications: EMVCo 3.1, NFC Forum


Quick reference to our documentation types.

1-5 of 13 documents

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Design Resources

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Design Files

2 design files

  • Printed Circuit Boards and Schematics

    Module board PN5190 HVQFN design files

  • Printed Circuit Boards and Schematics

    Evaluation Board PNEV5190MB Design Files


3 hardware offerings


1-5 of 12 software files

  • Libraries

    NFC Reader Library v.06.10.00 for PN5190 I.MX1170

  • Operating Systems

    PN5190 B1 Firmware 2.07 and Firmware 2.F7new

  • Operating Systems

    PN5190 B2 Firmware 3.01 and Firmware 3.F1new

  • Operating Systems

    PN5190 B1 Firmware 2.06 and Firmware 2.F6 (REV 1.4)

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Note: For better experience, software downloads are recommended on desktop.


3 trainings


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