eIQ™ for TensorFlow Lite

Overview

Integrated in MCUXpresso and Yocto development environments, eIQ delivers TensorFlow Lite for NXP’s MCU and MPU platforms. Developed by Google to provide reduced implementations of TensorFlow (TF) models, TF Lite uses many techniques for achieving low latency such as pre-fused activations and quantized kernels that allow smaller and (potentially) faster models. Furthermore, like TensorFlow, TF Lite utilizes the Eigen library to accelerate matrix and vector arithmetic.

TF Lite defines a model file format, based on FlatBuffers. Unlike TF’s protocol buffers, FlatBuffers have a memory footprint an order of magnitude smaller allowing better use of cache lines, leading to faster execution on NXP devices. Although TF Lite supports a subset of TF neural network operations, it still maintains a wide range of supported operations (~50), thereby allowing the use of more advanced models compared to CMSIS-NN. It also supports recurrent neural networks (RNNs) and the even more complex long short-term memory (LSTM) cells.

Features

Delivered as middleware in NXP MCUXpresso SDK (release 2.6.0) and Yocto BSP releases
NXP eIQ support available for i.MX RT crossover MCUs and i.MX Apps Processors
Provides the ability to run inferencing on Arm^® Cortex^®-M, Cortex-A, Verisilicon GPUs and NPU
Faster and smaller than TensorFlow — enables inference at the edge with lower latency and smaller binary size
Uses open source libraries to accelerate matrix and vector arithmetic (Eigen and GEMMLOWP)
NXP optimized implementation of GEMMLOWP uses Arm^® Cortex^®-M7 SIMD instructions yielding 2-3x performance increase compared to out-of-the-box implementation

Features

Delivered as middleware in NXP MCUXpresso SDK (release 2.6.0) and Yocto BSP releases
NXP eIQ support available for i.MX RT crossover MCUs and i.MX Apps Processors
Provides the ability to run inferencing on Arm^® Cortex^®-M, Cortex-A, Verisilicon GPUs and NPU
Faster and smaller than TensorFlow — enables inference at the edge with lower latency and smaller binary size
Uses open source libraries to accelerate matrix and vector arithmetic (Eigen and GEMMLOWP)
NXP optimized implementation of GEMMLOWP uses Arm^® Cortex^®-M7 SIMD instructions yielding 2-3x performance increase compared to out-of-the-box implementation

Supported Devices

Processors and Microcontrollers
- Arm Processors
  - i.MX 6 Series Applications Processors: Multicore, Arm^® Cortex^®-A7 Core, Cortex-A9 Core, Cortex-M4 Core
    - i.MX6QP: i.MX 6QuadPlus Processor - Quad-Core, High-Performance, Advanced 3D Graphics, HD Video, Advanced Multimedia, Arm^® Cortex^®-A9 Core
    - i.MX6DL: i.MX 6DualLite Processors – Dual-Core, 3D Graphics, HD Video, Arm^® Cortex^®-A9 Core
    - i.MX6UL: i.MX 6UltraLite Processor - Low-power, secure, Arm^® Cortex^®-A7 Core
    - i.MX6Q: i.MX 6Quad Processors - High-Performance, 3D Graphics, HD Video, Arm^® Cortex^®-A9 Core
    - i.MX6SLL: i.MX 6SLL Processors - Single-Core Processor with Arm^® Cortex^®-A9 Core
    - i.MX6SX: i.MX 6SoloX Processors - Heterogeneous Processing with Arm^® Cortex^®-A9 and Cortex-M4 cores
    - i.MX6ULL: i.MX 6ULL Single-Core Processor with Arm^® Cortex^®-A7 Core
    - i.MX6S: i.MX 6Solo Processors – Single-Core, Multimedia, 3D Graphics, Arm^® Cortex^®-A9 Core
    - i.MX6D: i.MX 6Dual Processors - Dual-Core, 3D Graphics, HD Video, Multimedia, Arm^® Cortex^®-A9 Core
    - i.MX6SL: i.MX 6SoloLite Processors – Single-Core, Low-Power, EPD Controller, Arm^® Cortex^®-A9 Core
    - i.MX6DP: i.MX 6DualPlus Processor - Dual-Core, High-Performance, Advanced 3D Graphics, HD Video, Advanced Multimedia, Arm^® Cortex^®-A9 Core
  - i.MX 8 Series Applications Processors: Multicore Arm^® Cortex^®-A72, Cortex-A53, Cortex-A35, Cortex-M4, Cortex-M7 cores
    - i.MX8M: i.MX 8M Family - Arm^® Cortex^®-A53, Cortex-M4, Audio, Voice, Video
    - i.MX8: i.MX 8 Family – Arm^® Cortex^®-A53, Cortex-A72, Virtualization, Vision, 3D Graphics, 4K Video
    - i.MX8MMINI: i.MX 8M Mini - Arm^® Cortex^®-A53, Cortex-M4, Audio, Voice, Video
    - i.MX8MNANO: i.MX 8M Nano - Arm^® Cortex^®-A53, Cortex-M7
    - i.MX8X: i.MX 8X Family – Arm^® Cortex^®-A35, 3D Graphics, 4K Video, DSP, Error Correcting Code on DDR
  - i.MX 7 Series Applications Processors: Multicore Arm^® Cortex^®-A7, Cortex-M4
    - i.MX7ULP: i.MX 7ULP Family: Ultra-Low-Power with Graphics
    - i.MX7D: i.MX 7Dual Processors - Heterogeneous Processing with dual Arm^® Cortex^®-A7 cores and Cortex-M4 core
    - i.MX7S: i.MX 7Solo Processors - Heterogeneous Processing with Arm^® Cortex^®-A7 and Cortex-M4 cores
- Arm Microcontrollers
  - i.MX RT Crossover MCUs
    - i.MX-RT1015: i.MX RT1015 Crossover MCU with Arm^® Cortex^®-M7 core
    - i.MX-RT1020: i.MX RT1020 Crossover MCU with Arm^® Cortex^®-M7 core
    - i.MX-RT1064: i.MX RT1064 Crossover MCU with Arm^® Cortex^®-M7 core
    - i.MX-RT600: i.MX RT600 Crossover MCU with Arm^® Cortex^®-M33 and DSP Cores
    - i.MX-RT1060: i.MX RT1060 Crossover MCU with Arm^® Cortex^®-M7 core
    - i.MX-RT1050: i.MX RT1050 Crossover MCU with Arm^® Cortex^®-M7 core
    - i.MX-RT1010: i.MX RT1010 Crossover MCU with Arm^® Cortex^®-M7 core
  - LPC5500 Series: World’s Arm^® Cortex^®-M33 based Microcontroller Series for Mass Market, Leveraging 40nm Embedded Flash Technology
    - LPC55S6x: High Efficiency Arm^® Cortex^®-M33-based Microcontroller Family

What's New

Application Note

Application Note: Handwritten Digit Recognition Using TensorFlow Lite on i.MX RT1060 MCUs

This application note focuses on handwritten digit recognition on embedded systems through deep learning, using i.MX RT1060 MCUs, MCUXpresso SDK and eIQ™ technology.

Keep reading

eIQ™ for TensorFlow Lite

Overview

Features

eIQ™ TensorFlow Lite

eIQ™ TensorFlow Lite

Supported Devices

What's New

What's New

Application Note: Handwritten Digit Recognition Using TensorFlow Lite on i.MX RT1060 MCUs

eIQ^™ for TensorFlow Lite

eIQ^™ TensorFlow Lite

eIQ^™ TensorFlow Lite