I²C-Bus Repeater

Product Details

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Block Diagram

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PCA9515 Block Diagram

PCA9515 Block Diagram

Block diagram: PCA9515D, PCA9515DP

Features

Key Features

  • 2 channel, bidirectional buffer
  • I²C-bus and SMBus compatible
  • Active HIGH repeater enable input
  • Open-drain input/outputs
  • Lock-up free operation
  • Supports arbitration and clock stretching across the repeater
  • Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple controllers
  • Powered-off high-impedance I²C-bus pins
  • Operating supply voltage range of 3.0 V to 3.6 V
  • 5.5 V tolerant I²C-bus (SCLn, SDAn) and enable (EN) pins
  • 0 Hz to 400 kHz clock frequency1
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO8 and TSSOP8 (MSOP8)
  • The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater

Documentation

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Design Resources

Design Files

2 design files

Hardware

2 hardware offerings

Engineering Services

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