I2C-Bus Repeater

Product Details

Select a section:

Block Diagram

Choose a diagram:

PCA9515 Block Diagram

PCA9515 Block Diagram

PCA9515D, PCA9515DP Block Diagram


Key Features

  • 2 channel, bidirectional buffer
  • I2C-bus and SMBus compatible
  • Active HIGH repeater enable input
  • Open-drain input/outputs
  • Lock-up free operation
  • Supports arbitration and clock stretching across the repeater
  • Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple controllers
  • Powered-off high-impedance I2C-bus pins
  • Operating supply voltage range of 3.0 V to 3.6 V
  • 5.5 V tolerant I2C-bus (SCLn, SDAn) and enable (EN) pins
  • 0 Hz to 400 kHz clock frequency1
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO8 and TSSOP8 (MSOP8)
  • The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater


Quick reference to our documentation types.

1-5 of 19 documents

Show All

Design Resources

Design Files

2 design files

  • Models

    PCA9515 IBIS model

  • Symbols and Footprints

    PCA9515DP-TSSOP8-CAD Symbol and PCB Footprint – BXL File


2 hardware offerings

Engineering Services

2 engineering services

To find a complete list of our partners that support this product, please see our Partner Marketplace.


What do you need help with?