13-Bit GTL-/GTL/GTL+ to LVTTL Translator

GTL2006PW
  • Archived
  • This page contains information on a product that is no longer manufactured (discontinued). Specifications and information herein are available for historical reference only.

The GTL2006 is a 13-bit translator to interface between the 3.3 V LVTTL chip set I/O and the XeonTM processor GTL-/GTL/GTL+ I/O. The GTL2006 is designed for platform health management in dual processor applications.

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Product Details

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Block Diagram

Block diagram: GTL2006PW

GTL2006PW Block Diagram
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Features

Key Features

  • Operates as a GTL-/GTL/GTL+ to LVTTL sampling receiver or LVTTL to GTL-/GTL/GTL+ driver
  • 3.0 V to 3.6 V operation
  • LVTTL I/O not 5 V tolerant
  • Series termination on the LVTTL outputs of 30 Ω
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 250 V CDM per JESD22-C101
  • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 500 mA
  • Package offered: TSSOP28

Documentation

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Design Resources

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Design Files

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2 design files

  • Models

    GLT2006 IBIS model

    IBSRev 1.0Sep 9, 2014 00:00:0082.4 KBGTL2006_1
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  • Symbols and Footprints

    GTL2006PW_TSSOP28-CAD Symbol and PCB Footprint – BXL File

    ZIPRev 1May 21, 2020 10:06:0040.3 KBGTL2006PW-TSSOP28-BXL
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