Design Files
2 design files
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Models
GLT2006 IBIS model
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Symbols and Footprints
GTL2006PW_TSSOP28-CAD Symbol and PCB Footprint – BXL File
The GTL2006 is a 13-bit translator to interface between the 3.3 V LVTTL chip set I/O and the XeonTM processor GTL-/GTL/GTL+ I/O. The GTL2006 is designed for platform health management in dual processor applications.
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