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The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive LOW-output-impedance (100 mA/12 Ω) with LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL logic level translation.
The device is configured as two 8-bit transceivers that share a common clock and a leader output enable pin, but also have individual latch timing and output enable signals. D-type flip-flops and D-type latches enable three modes of data transfer; Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The combination of reduced output swing, reduced input threshold levels and configurable edge control provides the higher speed operation of GTL/GTL+ backplanes.
The GTL1655 can be used at GTL (VTT= 1.2 V, VREF= 0.8 V) or GTL+ (VTT= 1.5 V, VREF= 1.0 V) signalling levels. Port A and the control inputs are compliant with LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or GTL+ signal levels, with VREF providing the reference voltage input.
The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA) and the clock pin (CP) are used to control the data flow through the two 8-bit transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control pins nLEBA, nOEBA and CP in the same way, data flow from Port B to Port A can be controlled. The OE pin can be used to disable all of the I/O pins.
To optimize signal integrity, the GTL1655 features an adjustable edge rate control (VERC). By adjusting VERC between GND and VCC, a designer can adjust the Port B edge rate to suit an application?s load conditions.
The GTL1655 permits true live insertion capability by incorporating:
- BIAS VCC , to pre-charge outputs and avoid disturbing active data during card insertion.
- Ioff to disable current flow through powered-off I/Os.
- Power-up 3-state, which ensures outputs are high-impedance during power-up, thus preventing bus contention issues. Once VCC is above 1.5 V, the power-up 3-state circuit relinquishes control of the outputs to the OE pin. To ensure the outputs remain 3-state, the OE pin should be tied to VCC via a pull-up resistor.