3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter (DUART)

  • Archived
  • This page contains information on a product that is no longer manufactured (discontinued). Specifications and information herein are available for historical reference only.

Product Details

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Block Diagram

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SC28L92 Block Diagram

SC28L92A1A, SC28L92A1B


Key Features

  • Member of IMPACT family: 3.3 V to 5.0 V, -40 Cel to +85 Cel and 68xxx or 80xxx bus interface for all devices
  • Dual full-duplex independent asynchronous receiver/transmitters
  • 16 character FIFOs for each receiver and transmitter
  • Pin programming selects 68xxx or 80xxx bus interface
  • 16-bit programmable counter/timer
  • Programmable baud rate for each receiver and transmitter
  • 28 fixed rates: 50 kBd to 230.4 kBd
  • Other baud rates to 1 MHz at 16x
  • Programmable user-defined rates derived from a programmable counter/timer
  • External 1x or 16x clock
  • Parity, framing, and overrun error detection
  • False start bit detection
  • Line break detection and generation
  • Maximum data transfer rates: 1x - 1 Mbit/s, 16x - 1 Mbit/s
  • Automatic wake-up mode for multi-drop applications
  • Start-end break interrupt/status
  • Detects break which originates in the middle of a character
  • On-chip crystal oscillator
  • Power-down mode
  • Receiver time-out mode
  • Single 3.3 V or 5 V power supply
  • Powers up to emulate SC26C92

Programmable Data Format

  • 5 data to 8 data bits plus parity
  • Odd, even, no parity or force parity
  • 1 stop, 1.5 stop or 2 stop bits programmable in 1/16-bit increments

Programmable Channel Mode

  • Normal (full-duplex)
  • Automatic echo
  • Local loopback
  • Remote loopback
  • Multi-drop mode (also called wake-up or 9-bit)

Multi-function 7-Bit Input Port (includes IACKN)

  • Can serve as clock or control inputs
  • Change of state detection on four inputs
  • Inputs have typically > 100 kΩ pull-up resistors
  • Change of state detectors for modem control

Multi-function 8-Bit Output Port

  • Individual bit set/reset capability
  • Outputs can be programmed to be status/interrupt signals
  • FIFO status for DMA interface

Versatile Interrupt System

  • Single interrupt output with eight maskable interrupting conditions
  • Output port can be configured to provide a total of up to six separate interrupt outputs that may be wire ORed
  • Each FIFO can be programmed for four different interrupt levels
  • Watchdog timer for each receiver


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Design Resources

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Design Files

2 design files

  • Symbols and Footprints

    SC28L92A1B-QFP44-CAD Symbol and PCB Footprint – BXL File

  • Symbols and Footprints

    SC28L92A1B-QFP4-CAD Symbol and PCB Footprint – BXL File


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