Principal features
- Supports 12-clock (default) or 6-clock mode selection via ISP or parallel programmer
- 6-clock/12-clock mode programmable "on-the-fly" by an SFR bit
- Peripherals (PCA, timers, UART) may use either 6-clock or 12-clock mode while the CPU is in 6-clock mode
- 128-B page erase for efficient use of code memory as non-volatile data storage
- 0 MHz to 40 MHz operating frequency in 12x mode, 20 MHz in 6x mode
- 16/32/64 kB of on-chip flash user-code memory with ISP and IAP
- 1 kB RAM
- SPI (Serial Peripheral Interface) and enhanced UART
- PCA (Programmable Counter Array) with PWM and capture/compare functions
- Three 16-bit timers/counters
Additional features
- Four 8-bit I/O ports
- WatchDog Timer (WDT)
- 30 ms page erase, 150 ms block erase
- PLCC44 and TQFP44 packages
- Ten interrupt sources with four priority levels
- Second DPTR register
- Low EMI mode (ALE inhibit)
- Power-down mode with external interrupt wake-up
- Idle mode
Comparison to P89C51RB2/RC2/RD2 devices
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SPI: The P89CV51RB2/RC2/RD2 devices have an SPI interface that was not present on the P89C51RB2/RC2/RD2 devices.
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Smaller block size: The page size decreased from 4 kB to 128 B. These smaller pages can be erased and reprogrammed using IAP function calls, which makes practical use of code memory for non-volatile data storage. A page is erased in 30 ms or less. IAP and ISP code both support 128-B page operations. The IAP and ISP code uses multiple page-erase operations to emulate the erasing of larger block sizes (8 kB and 16 kB) to maintain firmware compatibility.
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Status bit replaces Status byte: Automatic entry into ISP mode following a reset is now controlled by one status bit. Its operation is almost identical to that used by the previous devices, which was based on the zero/non-zero value of the status byte.
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Faster block erase: The erase time for the entire user-code memory of the P89CV51RB2/RC2/RD2 devices is 150 ms, which is a significant improvement.
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Larger RAM size: RAM size increased from 512 B to 1 kB.
